Norbert Juffa

6370637, Apr 9, 2002

Aug 5, 1999

09/370789

Stephan G. Meier - Sunnyvale CA
Norbert Juffa - San Jose CA
Frederick D. Weber - San Jose CA
Stuart F. Oberman - Sunnyvale CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 938

712215, 709104, 712222

A microprocessor with a floating point unit configured to efficiently allocate multi-pipeline executable instructions is disclosed. Multi-pipeline executable instructions are instructions that are not forced to execute in a particular type of execution pipe. For example, junk ops are multi-pipeline executable. A junk op is an instruction that is executed at an early stage of the floating point units pipeline (e. g. , during register rename), but still passes through an execution pipeline for exception checking. Junk ops are not limited to a particular execution pipeline, but instead may pass through any of the microprocessors execution pipelines in the floating point unit. Multi-pipeline executable instructions are allocated on a per-clock cycle basis using a number of different criteria. For example, the allocation may vary depending upon the number of multi-pipeline executable instructions received by the floating point unit in a single clock cycle.

6374345, Apr 16, 2002

Jul 22, 1999

09/359919

Norbert Juffa - San Jose CA
Stuart F. Oberman - Sunnyvale CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 700

712220, 712222

An apparatus and method for handling tiny numbers using a super sticky bit are provided. In response to detecting that a preliminary result of an instruction corresponds to a tiny number and an underflow exception is masked, an execution pipeline can be configured to store a value corresponding to the preliminary result and a super sticky bit in a destination register. Also, a destination register tag corresponding to the destination register and a denormal exception indicator corresponding to the tiny number and masked underflow exception can be stored. A trap handler can be initiated to generate a corrected result for the instruction. The trap handler can detect that the denormal exception indicator has been set and can read the value and the super sticky bit from the destination register using the destination register tag. The trap handler can generate a corrected result for the instruction based on the value and the super sticky bit. An instruction subsequent to the trapping instruction can then be restarted.

6381625, Apr 30, 2002

Feb 12, 2001

09/782474

Stuart Oberman - Sunnyvale CA
Norbert Juffa - San Jose CA
Ming Siu - San Jose CA
Frederick D Weber - San Jose CA
Ravikrishna Cherukuri - Milpitas CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 7552

708606, D8605

A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated and used to create and select a number of partial products according to Booths algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines.

6393555, May 21, 2002

Aug 5, 1999

09/370787

Stephan G. Meier - Sunnyvale CA
Norbert Juffa - San Jose CA
Frederick D. Weber - San Jose CA
Stuart F. Oberman - Sunnyvale CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 930

712222, 712 32, 712 34, 712217, 712225

A microprocessor with a floating point unit configured to rapidly execute floating point compare (FCOMI) type instructions that are followed by floating point conditional move (FCMOV) type instructions is disclosed. FCOMI-type instructions, which normally store their results to integer status flag registers, are modified to store a copy of their results to a temporary register located within the floating point unit. If an FCMOV-type instruction is detected following an FCOMI-type instruction, then the FCMOV-type instructions source for flag information is changed from the integer flag register to the temporary register. FCMOV-type instructions are thereby able to execute earlier because they need not wait for the integer flags to be read from the integer portion of the microprocessor. A computer system and method for rapidly executing FCOMI-type instructions followed by FCMOV-type instructions are also disclosed.

6397238, May 28, 2002

Feb 12, 2001

09/782475

Stuart Oberman - Sunnyvale CA
Norbert Juffa - San Jose CA
Ming Siu - San Jose CA
Frederick D Weber - San Jose CA
Ravikrishna Cherukuri - Milpitas CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 752

708497, 708551

A multiplier capable of performing signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. An effective sign for the multiplier and multiplicand operands may be calculated and used to create and select a number of partial products according to Booths algorithm. Once the partial products have been created and selected, they may be summed and the results may be output. The results may be signed or unsigned, and may represent vector or scalar quantities. When a vector multiplication is performed, the multiplier may be configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components. The multiplier may also be configured to sum the products of the vector components to form the vector dot product. The final product may be output in segments so as to require fewer bus lines.

6397239, May 28, 2002

Feb 6, 2001

09/778352

Stuart F. Oberman - Sunnyvale CA
Norbert Juffa - San Jose CA
Fred Weber - San Jose CA
Krishnan Ramani - Sunnyvale CA
Ravi Krishna Cherukuri - Milpitas CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 742

708505, 708495

A multimedia execution unit configured to perform vectored floating point and integer instructions. The execution unit may include an add/subtract pipeline having far and close data paths. The far path is configured to handle effective addition operations and effective subtraction operations for operands having an absolute exponent difference greater than one. The close path is configured to handle effective subtraction operations for operands having an absolute exponent difference less than or equal to one. The close path is configured to generate two output values, wherein one output value is the first input operand plus an inverted version of the second input operand, while the second output value is equal to the first output value plus one. Selection of the first or second output value in the close path effectuates the round-to-nearest operation for the output of the adder.

6405305, Jun 11, 2002

Sep 10, 1999

09/394024

Stephan G. Meier - Mountain View CA
Jeffrey E. Trull - San Jose CA
Derrick R. Meyer - Austin TX
Norbert Juffa - San Jose CA

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 9302

712222, 712226, 712221, 712224, 712245, 712217, 712227, 708510

A microprocessor with a floating point unit configured to rapidly execute floating point load control word (FLDCW) type instructions in an out of program order context is disclosed. The floating point unit is configured to schedule instructions older than the FLDCW-type instruction before the FLDCW-type instruction is scheduled. The FLDCW-type instruction acts as a barrier to prevent instructions occurring after the FLDCW-type instruction in program order from executing before the FLDCW-type instruction. Indicator bits may be used to simplify instruction scheduling, and copies of the floating point control word may be stored for instruction that have long execution cycles. A method and computer configured to rapidly execute FLDCW-type instructions in an out of program order context are also disclosed.

6408379, Jun 18, 2002

Jun 10, 1999

09/329718

Norbert Juffa - San Jose CA
Stephan Meier - Sunnyvale CA
Stuart Oberman - Sunnyvale CA
Scott White - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

G06F 738

712222, 712217, 712218, 708498

An apparatus and method for executing floating-point store instructions in a microprocessor is provided. If store data of a floating-point store instruction corresponds to a tiny number and an underflow exception is masked, then a trap routine can be executed to generate corrected store data and complete the store operation. In response to detecting that store data corresponds to a tiny number and the underflow exception is masked, the store data, store address information, and opcode information can be stored prior to initiating the trap routine. The trap routine can be configured to access the store data, store address information, and opcode information. The trap routine can be configured to generate corrected store data and complete the store operation using the store data, store address information, and opcode information.