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Nikhil A Kelkar

from New Market, MD
Age ~45
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Also known as:
Nikhi Kelkar
Related to:
Nikhi KelkarVaishali Kelkar
Connected to:
Amrita Kelkar, 36Anand A Kelkar, 48Aniruddha V Kelkar, 35Arti Kelkar, 49Ashutosh Kelkar, 42Jesse A Kelkar, 43Kuldeep P Kelkar, 47Sandeep B Kelkar, 53Suntosh N Kelkar, 43Vinayak P Kelkar, 54

Nikhil Kelkar Phones & Addresses

  • New Market, MD
  • Frisco, TX
  • Walnut Creek, CA
  • Union City, CA
  • Nutley, NJ
  • Reisterstown, MD
  • Cleveland, OH
  • Columbia, MD
  • Las Vegas, NV
  • Jersey City, NJ

Publications

Us Patents

Method And Apparatus For Forming An Underfill Adhesive Layer

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US Patent:
6352881, Mar 5, 2002
Filed:
Jul 22, 1999
Appl. No.:
09/359214
Inventors:
Luu Nguyen - Sunnyvale CA
Nikhil Kelkar - Santa Clara CA
Christopher Quentin - Fremont CA
Ashok Prabhu - Sunnyvale CA
Hem P. Takiar - Fremont CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 2144
US Classification:
438108, 438114, 438118, 438612, 257758, 257783, 257778, 257779
Abstract:
A method and apparatus for forming a layer of underfill adhesive on an integrated circuit located on a wafer surface are described. As a flip chip, the integrated circuit has electrically conductive pads, most of which have a solder ball attached thereto. A layer of underfill adhesive is then formed on the wafer surface such that at least some portion of most of the solder balls remain uncovered. The layer of underfill adhesive is partially cured and the flip chip is then mounted onto a substrate. A solder reflow operation electrically couples the flip chip and the substrate as well as fully cures the underfill adhesive.

Universal Tape For Integrated Circuits

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US Patent:
6398034, Jun 4, 2002
Filed:
Feb 29, 2000
Appl. No.:
09/515588
Inventors:
Hem P. Takiar - Fremont CA
Nikhil Vishwanath Kelkar - Santa Clara CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
B65D 8500
US Classification:
206716, 206722, 206486
Abstract:
The present invention provides a low cost carrier tape designed to store chips during transportation. The invention comprises a carrier tape which contains receptacle holes designed to secure chips onto the carrier tape by clasping onto the chips electrical contacts. The receptacle holes prevent the chip from rotating and physically moving. The receptacle holes are formed in patterns to match the standardized electrical contact patterns of flip chip families. The diameters of the receptacle holes may be sized slightly smaller than the diameter of electrical contacts such that a chip is secured by âsnap-fittingâ each electrical contact into a receptacle hole. Relief slits may be formed on the edges of the receptacle holes to facilitate the âsnap-fittingâ of electrical contacts into receptacle holes.

Metal Coated Markings On Integrated Circuit Devices

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US Patent:
6448632, Sep 10, 2002
Filed:
Aug 28, 2000
Appl. No.:
09/649264
Inventors:
Hem P. Takiar - Fremont CA
Nikhil Vishwanath Kelkar - Santa Clara CA
Ken Pham - San Jose CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 23552
US Classification:
257659, 257678
Abstract:
A semiconductor device comprising a mark located on a surface of the semiconductor device and a metal layer covering the marked surface and the mark. The metal layer functions to protect the semiconductor device from exposure to electromagnetic radiation and allows the mark to be visible for identification purposes. The present invention also pertains a method of manufacturing the semiconductor device as described. The method involves forming a mark on a semiconductor substrate surface of the device and covering the semiconductor substrate surface and the mark with a layer of metal so that the device is protected from exposure to electromagnetic radiation and allows the mark to be visible for identification purposes.

Method Of Packaging Fuses

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US Patent:
6459143, Oct 1, 2002
Filed:
Apr 26, 2001
Appl. No.:
09/844062
Inventors:
Inderjit Singh - San Jose CA
Hem P. Takiar - Fremont CA
Ranjan J. Mathew - San Jose CA
Nikhil V. Kelkar - Santa Clara CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 2358
US Classification:
257665, 257666, 257676, 257686, 257685, 257669
Abstract:
Improved methods of packaging external fuses together with integrated circuit devices are described. A pair of frame strips are provided that each have an associated set of contact pads. A resistor paste is applied to one of the contact pad sets and the frame strips are laminated together by curing the resistor paste which is positioned between the contact pad sets. Dice are mounted to the opposite sides of the second contact pads to form integrated circuit devices having integrally packaged external fuses. The packaged devices are eventually singulated for use. In some embodiments, the contact pads each have downturned tabs that form wings on opposite sides of each die. When the dice are flip chips, a device may be attached to a substrate board by soldering both the bumps on the die and the tab wing tips to the substrate board. In a preferred embodiment, the resistor paste is a positive temperature coefficient resistor paste.

Barrier Pad For Wafer Level Chip Scale Packages

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US Patent:
6462426, Oct 8, 2002
Filed:
Dec 14, 2000
Appl. No.:
09/738122
Inventors:
Nikhil Vishwanath Kelkar - San Jose CA
Stephen A. Gee - Danville CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 2348
US Classification:
257781, 257761, 257737, 257762
Abstract:
An integrated circuit device comprising a semiconductor die having a plurality of conductive pads. Over the conductive pads is formed a passivation layer that has a plurality of passivation layer openings. The passivation layer openings are positioned over an associated one of the conductive pads. Barrier base pads are placed in electrical contact with the conductive pads such that a portion of each of barrier base pads cover at least the perimeter of each passivation layer opening. Each of the barrier base pads prevents cracks from propagating through the integrated circuit device. In another aspect of the invention, the integrated circuit device is attached to an external substrate by connecting the contact bumps to the bond pads on an electronic substrate. In yet another aspect of the invention, a method for manufacturing the integrated circuit device is described.

Front Side Coating For Bump Devices

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US Patent:
6468892, Oct 22, 2002
Filed:
Jul 14, 2000
Appl. No.:
09/616475
Inventors:
Mark Harrison Baker - San Jose CA
Nikhil Kelkar - San Jose CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 2144
US Classification:
438612
Abstract:
Flip chips with improved solder bump strength are provided. A solder mask layer is placed and patterned on a front side of a wafer of semiconductor chips with semiconductor devices and bond pads. The solder mask is patterned to expose the bond pads. Solder bumps are electrically connected to the bond pads. The solder mask is thick enough to extend up to at least a quarter of the solder bumps and is in contact with the solder bumps. The wafer is then cut into individual chips. The chips may be sold to customers, who may mount the chip on a substrate without underfill.

Front Side Coating For Bump Devices

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US Patent:
6566762, May 20, 2003
Filed:
Sep 4, 2002
Appl. No.:
10/235058
Inventors:
Mark Harrison Baker - San Jose CA
Nikhil Kelkar - San Jose CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 2940
US Classification:
257778, 257779, 257737
Abstract:
Flip chips with improved solder bump strength are provided. A solder mask layer is placed and patterned on a front side of a wafer of semiconductor chips with semiconductor devices and bond pads. The solder mask is patterned to expose the bond pads. Solder bumps are electrically connected to the bond pads. The solder mask is thick enough to extend up to at least a quarter of the solder bumps and is in contact with the solder bumps. The wafer is then cut into individual chips. The chips may be sold to customers, who may mount the chip on a substrate without underfill.

Chip Scale Package With Compliant Leads

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US Patent:
6521970, Feb 18, 2003
Filed:
Sep 1, 2000
Appl. No.:
09/653820
Inventors:
Hem P. Takiar - Fremont CA
Nikhil Vishwanath Kelkar - San Jose CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 2900
US Classification:
257522, 257784, 257776, 257758
Abstract:
A wafer level fabricated chip scale integrated circuit package having an air gap formed between the integrated circuit die of the package and compliant leads located over and conductively attached to the die is described. Contact bumps offset on the compliant leads provide for connection of the integrated circuit package to other substrates. In some embodiments, the compliant leads include a conductive layer overlaid with an outer resilient layer, and may further include an inner resilient layer beneath the conductive layer. The outer resilient layer has a via formed through it exposing the underlying conductive layer. The via is offset along the compliant lead a horizontal distance from the bond pad to which the compliant lead is conductively coupled. The chip scale package provides a highly compliant connection between the die and any substrate that the die is attached to.
Control profile
Nikhil A Kelkar from New Market, MD, age ~45 Get Report