Inventors:
Robert J. Gluss - Los Gatos CA
Nicholas S. Fiduccia - Saratoga CA
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
G06F 1750
US Classification:
716 8, 716 9, 716 10, 716 11
Abstract:
A method of integrating repeaters into an integrated circuit design model includes specifying a geometry of a plurality of separate cell blocks. These cell blocks are locations on a chip die supporting appropriate functional capabilities, such as arithmetic and logic functions, decoders, input/output, etc. A list identifying top level nets connecting the cell blocks is then generated and locations along these top level nets exceeding a maximum signal transmission criteria (e. g. , RC interconnect constraints) are identified. Repeater constraint regions are defined apart from the cell blocks and include one or more of the locations identified. A list is then generated of top level nets to be repeated at respective repeater constraint regions. An HDL representation is generated of repeater blocks for placement within each of the repeater constraint regions. Wiring directives may then be automatically generated connecting the HDL representation of repeater blocks into the integrated circuit design model.