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Newsha M Ardalani

from Los Angeles, CA
Age ~38
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Also known as:
Ardalani Newsha
Phone and address:
10724 Wilshire Blvd APT 310, Los Angeles, CA 90024
Related to:
Hamisha Ardalani, 38
Connected to:
Nima Ardalan, 59David E Ardale, 65Esther L Ardan, 87Gary S Ardan, 77Julius L Ardan, 92Barbara A Ardary, 75James Ardary, 66John M Ardary, 89Sally J Ardary, 62Emile A Ardashian, 45

Newsha Ardalani Phones & Addresses

  • 10724 Wilshire Blvd APT 310, Los Angeles, CA 90024
  • Santa Clara, CA
  • Sunnyvale, CA
  • Madison, WI

Publications

Us Patents

Systems And Methods For Stream-Dataflow Acceleration

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US Patent:
20190317770, Oct 17, 2019
Filed:
Apr 15, 2019
Appl. No.:
16/384819
Inventors:
- Madison WI, US
Anthony Nowatzki - Los Angeles CA, US
Vinay Gangadhar - Madison WI, US
Preyas Shah - Madison WI, US
Newsha Ardalani - Santa Clara CA, US
Assignee:
SimpleMachines Inc. - Madison WI
International Classification:
G06F 9/38
G06F 9/50
G06F 9/48
G06F 9/30
Abstract:
According to some embodiments, a dataflow accelerator comprises a control/command core, a scratchpad and a coarse grain reconfigurable array (CGRA). The scratchpad comprises a write controller to transmit data to an input vector port interface and to receive data from the input vector port interface. The CGRA receives data from the input vector port interface where the CGRA comprising a plurality of interconnects and a plurality of functional units.

Method Of Estimating Program Speed-Up In Highly Parallel Architectures Using Static Analysis

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US Patent:
20170270424, Sep 21, 2017
Filed:
Mar 15, 2016
Appl. No.:
15/070466
Inventors:
- Madison WI, US
Newsha Ardalani - Madison WI, US
Urmish Thakker - Madison WI, US
International Classification:
G06N 99/00
G06F 9/30
Abstract:
The amount of speed-up that can be obtained by optimizing the program to run on a different architecture is determined by static measurements of the program. Multiple such static measurements are processed by a machine learning system after being discretized to alter their accuracy vs precision. Static analysis requires less analysis overhead and permits analysis of program portions to optimize allocation of porting resources on a large program.

Method Of Estimating Program Speed-Up With Highly Parallel Architectures

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US Patent:
20150261536, Sep 17, 2015
Filed:
Mar 14, 2014
Appl. No.:
14/212711
Inventors:
- Madison WI, US
Newsha Ardalani - Madison WI, US
Xiaojin Zhu - Middleton WI, US
Assignee:
Wisconsin Alumni Research Foundation - Madison WI
International Classification:
G06F 9/30
G06F 9/445
G06N 99/00
Abstract:
The amount of speed-up that can be obtained by moving a program to a parallel architecture is determined by a model associating speed-up to micro-architecture independent features of the program execution. The model may be generated, for example, by linear regression, by evaluating programs that have been ported to parallel architectures where the micro-architecture independent features are known.
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Newsha M Ardalani from Los Angeles, CA, age ~38 Get Report