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Nevine Nassif

from Arlington, MA
Age ~67
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Also known as:
Nevine Kotiuga, Nevin Nassif, Nevine Nassis
Phone and address:
28 Stone Rd, Arlington, MA 02474
(781) 643-3160
Related to:
Natalie M Nassif, 27Jason R Nassif, 31
Connected to:
Ahdy A Nassif, 52Carlos G Nassif, 60Elizabeth A Nassif, 42Karen L Nassif, 78L Nassif, 31Nassif T Nassif, 56Ramy Nassif, 53Ronald J Nassif, 80Samer R Nassif, 44Guy Nassiff, 65

Nevine Nassif Phones & Addresses

  • 28 Stone Rd, Arlington, MA 02474 (781) 643-3160
  • 85 Brainerd Rd, Allston, MA 02134
  • Boston, MA
  • Brooklyn, NY

Work

Company: Intel Feb 2003 Position: Principal engineer

Education

Degree: Ph.D. School / High School: McGill University 1981 to 1985 Specialities: Electrical Engineering

Skills

Processors • Microprocessors • Vlsi • Soc • Asic • Debugging • Hardware Architecture • Eda • Ic • Semiconductors • Computer Architecture • Static Timing Analysis • Perl • Logic Design • Simulations • Algorithms • Circuit Design • Cmos • Intel • Signal Integrity • Timing Closure • Physical Design • Integrated Circuit Design • Low Power Design • Microarchitecture • Silicon • Semiconductor Industry • Microelectronics • Floorplanning • Spice • Formal Verification • Cadence Virtuoso • Digital Circuit Design • Place and Route • High Performance Computing • Timing

Industries

Semiconductors

Resumes

Resumes

Nevine Nassif Photo 1

Principal Engineer

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Location:
28 Stone Rd, Arlington, MA 02474
Industry:
Semiconductors
Work:
Intel since Feb 2003
Principal Engineer
Hewlett-Packard May 2002 - Feb 2003
Senior Member Technical Staff
Compaq Jun 1998 - May 2002
Senior Member Technical Staff
Digital Equipment Corporation May 1985 - Jun 1998
Principal Engineer
Education:
McGill University 1981 - 1985
Ph.D., Electrical Engineering McGill University 1979 - 1981
M.Eng, Electrical Engineering McGill University 1976 - 1979
B. Eng, Electrical Engineering
Skills:
Processors
Microprocessors
Vlsi
Soc
Asic
Debugging
Hardware Architecture
Eda
Ic
Semiconductors
Computer Architecture
Static Timing Analysis
Perl
Logic Design
Simulations
Algorithms
Circuit Design
Cmos
Intel
Signal Integrity
Timing Closure
Physical Design
Integrated Circuit Design
Low Power Design
Microarchitecture
Silicon
Semiconductor Industry
Microelectronics
Floorplanning
Spice
Formal Verification
Cadence Virtuoso
Digital Circuit Design
Place and Route
High Performance Computing
Timing

Publications

Us Patents

Method And Apparatus For Modeling Gate Capacitance Of Symmetrically And Asymmetrically Sized Differential Cascode Voltage Swing Logic (Dcvsl)

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US Patent:
6438732, Aug 20, 2002
Filed:
Apr 14, 1999
Appl. No.:
09/291345
Inventors:
James Arthur Farrell - Harvard MA
Nevine Nassif - Arlington MA
Gill Watt - Acton MA
Assignee:
Compaq Computer Corporation - Houston TX
International Classification:
G06F 1750
US Classification:
716 4, 716 5, 716 6
Abstract:
A method and apparatus for determining load capacitance of DCVSL circuits in timing verification of a circuit is disclosed in the present invention. The gate capacitances for various MOS devices are modeled based upon simulations with certain conditions for inputs to the gate, source and drain. The system then determines the existence of DCVSL circuits within the topology of a circuit, and applies one of several models to determine minimum and maximum capacitances for the encountered DCVSL structures. The determination of minimum and maximum capacitance depends upon the selected model and the capacitance of each of the MOS devices as previously calculated.

Timing Verifier For Mos Devices And Related Method

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US Patent:
6473888, Oct 29, 2002
Filed:
Dec 10, 1998
Appl. No.:
09/208780
Inventors:
Nevine Nassif - Arlington MA
Madhav Desai - Mumbai, IN
James Arthur Farrell - Harvard MA
Roy Badeau - Berlin MA
Nicholas Lee Rethman - North Andover MA
Assignee:
Compaq Computer Corporation - Houston TX
International Classification:
G06F 1750
US Classification:
716 6, 716 5, 716 4
Abstract:
The present invention relates to a method and apparatus for determining capacitance and charge models for MOS devices to be used in calculating delays in a timing verifier for a circuit. The models are generated by first creating a variety of configurations of MOS devices which vary the inputs to the source, drain, and gate. Such inputs may include rising and falling values as well as constant values at VDD and VSS. Simulations are run on all of the configurations using conditions anticipated for the circuit to be analyzed. Capacitance values obtained from the simulations are used to determine models based upon length and width of the MOS devices using standard curve fitting techniques. Models then can be used for determining delays within the circuit.

Method And Apparatus For Estimating Elmore Delays Within Circuit Designs

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US Patent:
6606587, Aug 12, 2003
Filed:
Apr 14, 1999
Appl. No.:
09/291721
Inventors:
Nevine Nassif - Arlington MA
Madhav Desai - Powai, IN
Dale Hayward Hall - Northborough MA
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 1750
US Classification:
703 14, 716 2, 716 5, 716 6, 716 8
Abstract:
A system for rapidly accurate Elmore delays is disclosed which uses circuit simulations with different circuit configurations to generate Elmore delay models. From data generated by the simulations, Elmore delays are represented as functions of a capacitance charge and device width for a variety of device configurations. Similarly, accurate capacitance models are determined for each device. To determine an Elmore delay for a discharge path, the appropriate models are applied to each device and summed together. Within a timing verifier, the present invention can rapidly determine critical paths which require additional consideration.

Method To Compress A Piecewise Linear Waveform So Compression Error Occurs On Only One Side Of The Waveform

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US Patent:
6654713, Nov 25, 2003
Filed:
Nov 22, 1999
Appl. No.:
09/447019
Inventors:
Nicholas L. Rethman - North Andover MA
Nevine Nassif - Arlington MA
William J. Grundmann - Westborough MA
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F 1750
US Classification:
703 19, 703 2, 703 5, 703 14
Abstract:
A method of data compression for continuous or piecewise linear curves in two variables is presented which can guarantee that any compression error is exclusively on one selected side of the curve. Limiting errors to one side is required when simulating integrated circuit performance to determine if a design will have speed-related problems. In such a simulation it is necessary to calculate both the minimum and maximum possible time delays for a logic chain of circuit elements. Data compression of the transistor or gate voltage versus time relationship is necessary to reduce the very large amount of data that is required for the simulation. Data compression may introduce errors into the data in either direction. If it is necessary to have any possible error confined to one side of the curve, the compressed data must be shifted toward the desired error side by at least the maximum possible data error. This shifting increases the total error between the compressed data and reality by more than is acceptable in current simulations.

Method And Apparatus For Performing Timing Verification Of A Circuit

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US Patent:
6658506, Dec 2, 2003
Filed:
Apr 14, 1999
Appl. No.:
09/292051
Inventors:
Nevine Nassif - Arlington MA
James Arthur Farrell - Harvard MA
Dale Hayward Hall - Northborough MA
Gill Watt - Acton MA
Assignee:
Compaq Computer Corporation - Houston TX
International Classification:
G06F 104
US Classification:
710 58, 713500, 455114, 375296
Abstract:
A system for accurately determining Elmore delays in DCVSL structures is disclosed. The system uses circuit simulation to determine models for Elmore delays through devices within specific circuit structures. The circuit structures include DCVSL circuits to accurately model performance of devices with such a structure. The system also determines discharge characteristics for DCVSL circuits using simulation. In order to determine Elmore delays, the system analyzes a circuit representation to locate DCVSL structures. The discharge characteristics and models are used to determine Elmore delays for each structure located.

Timing Verifier For Mos Devices And Related Method

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US Patent:
6877142, Apr 5, 2005
Filed:
Aug 13, 2002
Appl. No.:
10/218079
Inventors:
Nevine Nassif - Arlington MA, US
Madhav Desai - Mumbai, IN
James Arthur Farrell - Harvard MA, US
Roy Badeau - Berlin MA, US
Nicholas Lee Rethman - North Andover MA, US
Assignee:
Hewlett-Packard Development Company, L.P. - Houston TX
International Classification:
G06F017/50
US Classification:
716 6, 716 4, 716 5
Abstract:
The present invention relates to a method and apparatus for determining capacitances and charge models for MOS devices to be used in calculating delays in a timing verifier for a circuit. The models are generated by first creating a variety of configurations of MOS devices which vary the inputs to the source, drain, and gate. Such inputs may include rising and falling values as well as constant values at VDD and VSS. Simulations are run on all of the configurations using conditions anticipated for the circuit to be analyzed. Capacitance values obtained from the simulations are used to determine models based upon length and width of the MOS devices using standard curve fitting techniques. Models then can be used for determining delays within the circuit.

Pruning Of Short Paths In Static Timing Verifier

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US Patent:
60469846, Apr 4, 2000
Filed:
Apr 11, 1997
Appl. No.:
8/827868
Inventors:
Joel Joseph Grodstein - Mountain View CA
Nicholas L. Rethman - Hudson MA
Nevine Nassif - Arlington MA
Assignee:
Digital Equipment Corp. - Maynard MA
International Classification:
G01R 3108
H04L 1228
G06F 1500
US Classification:
370248
Abstract:
A conservative algorithm for pruning data paths during logic circuit timing verification is disclosed. It uses the correlation between delays on data paths and clock paths in order to prune non-critical data paths during the traversal of the network. Subnetworks are identified in the larger network. Pruning data consisting of the minimum possible delay across all possible paths through the subnetwork, the deskewing clocks, the clock arrival times, and hold times at the synchronizers in the subnetwork are identified the first time each subnetwork is analyzed. In later analysis, the pruning data stored for each subnetwork is used to determine whether a data path can be pruned. A path can be pruned if it is shown to be race-free based on the pruning data. In this way, non-critical paths need only be traced once during timing verification.

Functionally Redundant Semiconductor Dies And Package

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US Patent:
20210375825, Dec 2, 2021
Filed:
Aug 10, 2021
Appl. No.:
17/398831
Inventors:
- Santa Clara CA, US
Mark T. BOHR - Aloha OR, US
Udi SHEREL - Natanya, IL
Leonard M. NEIBERG - Portland OR, US
Nevine NASSIF - Arlington MA, US
Wesley D. MC CULLOUGH - Santa Clara CA, US
International Classification:
H01L 25/065
H01L 25/18
H01L 25/00
Abstract:
Systems and methods of providing redundant functionality in a semiconductor die and package are provided. A three-dimensional electrical mesh network conductively couples smaller semiconductor dies, each including circuitry to provide a first functionality, to a larger base die that includes circuitry to provide a redundant first functionality to the semiconductor die circuitry. The semiconductor die circuitry and the base die circuitry selectively conductively couple to a common conductive structure such that either the semiconductor die circuitry or the base die circuitry is able to provide the first functionality at the conductive structure. Driver circuitry may autonomously or manually, reversibly or irreversibly, cause the semiconductor die circuitry and the base die circuitry couple to the conductive structure. The redundant first functionality circuitry improves the operational flexibility and reliability of the semiconductor die and package.
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Nevine Nassif from Arlington, MA, age ~67 Get Report