Search

Neal L Horovitz

from Los Altos, CA
Age ~56
Get Report
Also known as:
Horovitz Lane Neal, Neil Horowitz
Phone and address:
2240 Homestead Ct, Los Altos, CA 94024
(408) 732-9663
Related to:
James R GrGeorge W O'Connor, 51Tracy L O'Connor, 52Marvin S Horovitz, 90Zelda HorovitzAmy M Stein, 86Glenna M Herman, 90Susan M Herman, 55
Connected to:
Elisha M Horovitz, 73Christopher A Horowicz, 55Nathalie C Horowicz, 48Abby E Horowitz, 76Arnona V Horowitz, 82Audrey S Horowitz, 62Ave D Horowitz, 53Aviva Y Horowitz, 39Avraham D Horowitz, 47Brook L Horowitz, 30

Neal Horovitz Phones & Addresses

  • 2240 Homestead Ct, Los Altos, CA 94024 (408) 732-9663 (408) 774-9308
  • 2240 Homestead Ct APT 107, Los Altos, CA 94024 (408) 732-9663
  • 655 Fair Oaks Ave, Sunnyvale, CA 94086 (408) 732-9663
  • Winchester, MA
  • 2240 Homestead Ct APT 107, Los Altos, CA 94024 (415) 441-8454

Work

Company: Qualcomm Jun 2012 Position: Senior staff design engineer

Education

Degree: Master of Science, Masters School / High School: Santa Clara University 1997 to 2001 Specialities: Management, Engineering

Skills

Ic • Mixed Signal • Microcontrollers • Simulation • Debugging • Power Management • Semiconductors • Asic • Verilog • Hardware Design • Vlsi • Rtl Design • Digital Design

Languages

English

Interests

Exercise • Investing • Medicine • Electronics • Home Improvement • Reading • Crafts • Fitness • Cats • Travel • Collecting • Home Decoration • Health

Emails

n***[email protected]

Industries

Semiconductors

Resumes

Resumes

Neal Horovitz Photo 1

Senior Staff Design Engineer

View page
Location:
2240 Homestead Ct, Los Altos, CA 94024
Industry:
Semiconductors
Work:
Qualcomm
Senior Staff Design Engineer
Summit Microelectronics Feb 2011 - Jun 2012
Digital Design Engineer
Summit Microelectronics Oct 2009 - Feb 2011
Consultant - Digital Design Engineer
National Semiconductor 2002 - 2009
Staff Design Engineer
National Semiconductor 1998 - 2002
Senior Design Engineer
Education:
Santa Clara University 1997 - 2001
Master of Science, Masters, Management, Engineering Carnegie Mellon University 1986 - 1990
Bachelors, Bachelor of Science, Computer Engineering Winchester High School
Skills:
Ic
Mixed Signal
Microcontrollers
Simulation
Debugging
Power Management
Semiconductors
Asic
Verilog
Hardware Design
Vlsi
Rtl Design
Digital Design
Interests:
Exercise
Investing
Medicine
Electronics
Home Improvement
Reading
Crafts
Fitness
Cats
Travel
Collecting
Home Decoration
Health
Languages:
English

Publications

Us Patents

Power Conservation System And Method

View page
US Patent:
7184798, Feb 27, 2007
Filed:
Oct 3, 2002
Appl. No.:
10/264216
Inventors:
Gary A. Brown - Fremont CA, US
Neal Lane Horovitz - Los Altos CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H04B 1/38
H04M 1/00
US Classification:
455574, 4553455, 455344, 4553431, 4553432, 4551275, 4551803, 327156, 327143, 327108, 713322, 713324, 713501, 331 74, 331 96, 331 57, 331158
Abstract:
A power management circuit is arranged to apply power to and remove power from its own oscillator to conserve power. A power-on reset circuit provides a power-on-reset signal to a state machine. The state machine contains states that are programmed with information that is used to power up or down various subsystems within a device that includes the power management systems, including the oscillator of the state machine. The state machine assumes a known state and applies power to the oscillator in response to the power-on-reset signal. The state machine changes states in response to system events (e. g. , a keypress). The state machine also maintains power to the oscillator during the period of time and which the state machine requires clock signal from the oscillator. The state machine can power down the oscillator to conserve power when the state machine does not require a clock signal from the oscillator.

Battery Charger That Employs Current Sharing To Simultaneously Power An Application And Charge A Battery

View page
US Patent:
7535195, May 19, 2009
Filed:
Aug 25, 2005
Appl. No.:
11/212171
Inventors:
Neal Lane Horovitz - Los Altos CA, US
Luan Vu - San Jose CA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01M 6/50
US Classification:
320106, 320141, 320145
Abstract:
Circuitry for powering a load and charging of a battery from a power source by a smart power supply is provided. The smart power supply controls the maximum current for battery charging based in part upon variables such as the maximum rate of charge of the battery and maximum source current. The smart power supply is thus capable of providing the power requested by the load, and use the remaining power for battery charging.

Brownout And Power-Up Reset Signal Generator

View page
US Patent:
51592177, Oct 27, 1992
Filed:
Jul 29, 1991
Appl. No.:
7/737160
Inventors:
Gordon L. Mortensen - San Jose CA
Neal L. Horovitz - Sunnyvale CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H03K 513
H03K 301
H03K 1700
H02H 324
US Classification:
307597
Abstract:
A brownout reset generator includes a presettable counter and a reset controller consisting of a plurality of logic gates coupled to receive a brownout signal representing a power brownout condition or power assertion (i. e. power-up) and a clock signal, and to generate a brownout reset in response to and of selectively longer duration than the brownout signal. Following the leading edge of the brownout signal (i. e. initiation of the brownout condition), the counter is preset to a selected value and remains preset for the duration of the brownout signal. Following the trailing edge of the brownout signal (i. e. termination of the brownout condition), the counter begins counting clock pulses. The counter outputs a timing pulse after a selected number of clock pulses representing a predetermined time interval have been counted. The reset generator provides a brownout reset having a leading edge following and corresponding to the leading edge of the brownout signal and a trailing edge following and corresponding to the leading edge of the timing pulse.

Configurable Charge Controller

View page
US Patent:
20180129234, May 10, 2018
Filed:
Sep 13, 2017
Appl. No.:
15/703825
Inventors:
- San Diego CA, US
Christian Sporck - Campbell CA, US
Chunping Song - Sunnyvale CA, US
David Wong - Santa Clara CA, US
Rashed Hoque - Chandler AZ, US
Neal Horovitz - Los Altos CA, US
Hector Ivan Oporta - San Jose CA, US
Daryl Bergstrom - Chandler AZ, US
International Classification:
G05F 1/575
H02M 3/156
H02M 3/158
H02M 1/42
H02M 3/335
Abstract:
A configurable charge converter may include an adaptive low-dropout regulator. The adaptive low-dropout regulator may include a headroom detection circuit and a power supply controller. The headroom detection circuit may monitor a voltage drop across a field effect transistor (FET) and cause a programmable power supply to increase or decrease an output voltage accordingly. In some aspects, the configurable charge converter may include an adaptive low-dropout regulator and a buck/boost converter. The output power of the configurable charge controller may be provided by the adaptive low-dropout regulator, the buck/boost converter, or by both the adaptive low-dropout regulator and the buck/boost converter operating in combination.
Control profile
Neal L Horovitz from Los Altos, CA, age ~56 Get Report