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Naresh Maheshwari

from San Jose, CA
Age ~54
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Also known as:
Navesh Maheshwari
Phone and address:
429 Birkhaven Pl, San Jose, CA 95138
Related to:
Ramesh C MaheshwariSapna H Jain, 55Satya AgarwalMohit M Maheshwari, 50Sushil MaheshwariRashmi Maheshwari, 51Reeti Maheshwari, 50Asha Maheshwari, 73
Connected to:
Abhishek Maheshwari, 50Anshul Maheshwari, 38Arpan Maheshwari, 39Deepali Maheshwari, 41Gopal P Maheshwari, 78Jagdish Maheshwari, 61Rachna S Maheshwari, 46Radha K Maheshwari, 74Ramesh C Maheshwari, 67Richa Maheshwari, 41

Naresh Maheshwari Phones & Addresses

  • 429 Birkhaven Pl, San Jose, CA 95138
  • 4300 The Woods Dr, San Jose, CA 95136
  • 180 Elm Ct, Sunnyvale, CA 94086
  • Elmsford, NY
  • Ames, IA
  • Minneapolis, MN
  • Fremont, CA
  • 636 Chelsea Xing, San Jose, CA 95138

Resumes

Resumes

Naresh Maheshwari Photo 1

Principal Engineer, Fpga Prototying

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Location:
San Francisco, CA
Industry:
Computer Software
Work:
Synopsys 2010 - Jun 2015
Senior Staff Software Engineer
Synopsys 2010 - Jun 2015
Principal Engineer, Fpga Prototying
Magma Design Automation 2009 - 2010
Senior Architect, R and D
Envis 2008 - 2009
Principal Architect
Arm 2006 - 2008
Engineering Director, Software and Cad
Education:
University of California, Santa Cruz 2003 - 2005
Iowa State University 1994 - 1998
Doctorates, Doctor of Philosophy, Computer Engineering Indian Institute of Technology, Delhi 1992 - 1994
Master of Science, Masters, Engineering Motilal Nehru National Institute of Technology 1988 - 1992
Bachelors, Bachelor of Science, Computer Engineering
Skills:
Asic
Eda
Fpga
Static Timing Analysis
Soc
Arm
Tcl
Debugging
Low Power Design
Logic Synthesis
Software Development
Verilog
Semiconductors
Engineering Management
Vlsi
C
C++
Product Management
Perl
Microcontrollers
Computer Architecture
Naresh Maheshwari Photo 2

Naresh Maheshwari

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Naresh Maheshwari Photo 3

Naresh Maheshwari

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Naresh Maheshwari Photo 4

Naresh Maheshwari

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Publications

Isbn (Books And Publications)

Timing Analysis and Optimization of Sequential Circuits

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Author

Naresh Maheshwari

ISBN #

0792383214

Us Patents

Method And Apparatus For Circuit Design And Synthesis

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US Patent:
7131078, Oct 31, 2006
Filed:
Aug 21, 2003
Appl. No.:
10/646657
Inventors:
Naresh Maheshwari - San Jose CA, US
Kenneth S. McElvain - Los Altos CA, US
Assignee:
Synplicity, Inc. - Sunnyvale CA
International Classification:
G06F 17/50
US Classification:
716 3
Abstract:
Methods and apparatuses to maintain and propagate statistical data during circuit synthesis. At least one embodiment of the present invention maintains and propagates statistical data during and after circuit synthesis transformation operations. In one example, the signal switching activity is calculated once at the RTL level and then propagated and/or maintained at various nodes of the circuit through the process of logic synthesis. Thus, the statistical analysis of entire circuit during or after the logic synthesis is avoided. In one example, power optimization is performed during logic synthesis. A portion of the logic synthesis transformation is driven by the power consumption optimization; and, the statistical data about circuit activity maintained at the nodes of the circuit during the synthesis process is used to calculate the power consumption at various points in the process of synthesis transformation.
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Naresh Maheshwari from San Jose, CA, age ~54 Get Report