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Nabeel Shirazi

from Carlsbad, CA
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Connected to:
Abe Shirazi, 83Adnan M Shirazi, 78Asghar H Shirazi, 31Behrouz E Shirazi, 77Eimon Shirazi, 33Fernando M Shirazi, 56Rose Shirazi, 43Roxana S Shirazi, 39Shahid J Shirazi, 70Shahien M Shirazi, 41

Nabeel Shirazi Phones & Addresses

  • 18987 Mellon Dr, Saratoga, CA 95070
  • Millbrae, CA
  • Carlsbad, CA
  • Santa Clara, CA
  • 151 El Camino Real UNIT 406, Millbrae, CA 94030

Work

Company: Xilinx Jun 2013 Address: San Jose, CA Position: Director, system level design tools

Education

Degree: Ph.D. School / High School: Imperial College London 1995 to 1998 Specialities: Computing

Skills

Fpga • Verilog • Vhdl • Xilinx • Digital Signal Processors • Embedded Systems • C++ • Simulations • Modelsim • Linux • Hardware • System Generator • Algorithms • Xilinx Ise • Field Programmable Gate Arrays • Chipscope • C • Debugging • Signal Processing • Microprocessors • Matlab • Edk • Ise • Mathworks • Planahead • Synplify Pro • Microblaze • Soc • Software Development • Hardware Architecture • System on A Chip

Languages

English

Interests

Rowing

Industries

Semiconductors

Resumes

Resumes

Nabeel Shirazi Photo 1

Senior Director

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Location:
18987 Mellon Dr, Saratoga, CA 95070
Industry:
Semiconductors
Work:
Xilinx - San Jose, CA since Jun 2013
Director, System Level Design Tools
Xilinx since Nov 2010
Senior Engineering Manager
Xilinx Nov 2005 - Nov 2010
Senior Engineering Manager
Xilinx Nov 2000 - Nov 2005
Senior Staff Hardware/Software Engineer
Xilinx Nov 1998 - Nov 2000
Staff Software Engineer
Education:
Imperial College London 1995 - 1998
Ph.D., Computing Virginia Polytechnic Institute and State University 1993 - 1995
MSEE, Electrical Engineering The Ohio State University 1988 - 1993
BSEE, Electrical Engineering
Skills:
Fpga
Verilog
Vhdl
Xilinx
Digital Signal Processors
Embedded Systems
C++
Simulations
Modelsim
Linux
Hardware
System Generator
Algorithms
Xilinx Ise
Field Programmable Gate Arrays
Chipscope
C
Debugging
Signal Processing
Microprocessors
Matlab
Edk
Ise
Mathworks
Planahead
Synplify Pro
Microblaze
Soc
Software Development
Hardware Architecture
System on A Chip
Interests:
Rowing
Languages:
English

Publications

Us Patents

Method And Apparatus For Hardware Co-Simulation Clocking

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US Patent:
7085976, Aug 1, 2006
Filed:
Feb 18, 2003
Appl. No.:
10/370023
Inventors:
Nabeel Shirazi - San Jose CA, US
Singh Vinay Jitendra - Fremont CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G01R 31/28
US Classification:
714725, 714 30, 714733
Abstract:
Method and apparatus for hardware co-simulation clocking is described. More particularly, single-step clocking is used to load one or more test vectors and to output test results from such test vectors after processing. The test vectors are processed with the hardware using a free-running clock, for example to speed up test time and to generate information related to operational speed. A simulation of the hardware is used, where single-step clocking out the test results facilitates verification of the hardware test results with simulation test results.

Method And System For Modeling And Automatically Generating An Electronic Design From A System Level Environment

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US Patent:
7110935, Sep 19, 2006
Filed:
Oct 16, 2001
Appl. No.:
09/981503
Inventors:
L. James Hwang - Menlo Park CA, US
R. Brent Milne - Boulder CO, US
Nabeel Shirazi - Los Gatos CA, US
Jeffrey D. Stroomer - Lafayette CO, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
703 20, 703 22, 716 2, 716 5
Abstract:
Method and system for creating an electronic circuit design from a system-level environment. A plurality of user-selectable system-level design objects are provided in the system-level environment. Each system-level design object is defined by a system-level function and is selectable by a system-level designer. A plurality of hardware-level design objects are also provided. Each hardware-level design object is configured to generate a hardware definition of a hardware-level function. Each system-level design object maps to one or more hardware-level design objects. In response to selections made by the designer, a system-level design is instantiated in a system-level design file. The system-level design includes user-selected ones of the system-level design objects. The system simulates behavior of the system-level design consistent with both the system-level functions and behavior of a hardware definition from the hardware-level design objects that implement the user-selected ones of the system-level design objects.

Simulation Of Integrated Circuitry Within A High-Level Modeling System Using Hardware Description Language Circuit Descriptions

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US Patent:
7194705, Mar 20, 2007
Filed:
Mar 14, 2003
Appl. No.:
10/388692
Inventors:
Kumar Deepak - San Jose CA, US
L. James Hwang - Menlo Park CA, US
Singh Vinay Jitendra - Fremont CA, US
Haibing Ma - Superior CO, US
Roger B. Milne - Boulder CO, US
Nabeel Shirazi - San Jose CA, US
Jeffrey D. Stroomer - Lafayette CO, US
Jimmy Zhenming Wang - Saratoga CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 3, 716 5, 716 18, 716 7, 703 16
Abstract:
Method, apparatus, and computer readable medium for simulating an integrated circuit within a modeling system using one or more circuit description language representations of circuitry is described. By example, a circuit description language representation of the one or more circuit description language representations of circuitry is translated into a program language circuit description. A first simulation process is executed and input data is obtained therefrom. A second simulation process is executed with the input data as parametric input to produce output data, the second simulation process being derived from the program language circuit description. The output data produce by the second simulation process is provided to the first simulation process.

Vector Interface To Shared Memory In Simulating A Circuit Design

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US Patent:
7343572, Mar 11, 2008
Filed:
Mar 31, 2005
Appl. No.:
11/096024
Inventors:
Joshua Ian Stone - Santa Clara CA, US
Jonathan B. Ballagh - Longmont CO, US
Roger B. Milne - Boulder CO, US
Nabeel Shirazi - San Jose CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
716 4, 716 5, 716 6, 703 14
Abstract:
A first block, a second block, a shared memory, and a third block are generated in a circuit design in response to user input control. The first block is coupled to the second block, the second block is coupled to the shared memory, and the shared memory is coupled to the third block in response to user input control. During one cycle of a simulation, the second block, in response to the first block, accesses a set of scalar values in the shared memory using scalar accesses. During one cycle of the simulation, the set of scalar values is transferred between the second block and the first block. During the simulation, the shared memory is accessed by the third block using scalar accesses.

Vector Transfer During Co-Simulation

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US Patent:
7376544, May 20, 2008
Filed:
Feb 12, 2004
Appl. No.:
10/777419
Inventors:
Christopher H. Dick - San Jose CA, US
Nabeel Shirazi - San Jose CA, US
Roger B. Milne - Boulder CO, US
Jeffrey D. Stroomer - Lafayette CO, US
Jonathan B. Ballagh - Longmont CO, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
703 14, 716 4, 716 5
Abstract:
Various embodiments are disclosed for transferring data between blocks in a design during simulation. Operation of at least one high-level block in the design is simulated in a high-level modeling system (HLMS). A hardware-implemented block in the design is co-simulated on a hardware simulation platform. A first vector of data received by a co-simulation block is transferred to the simulated hardware-implemented block via a transfer function.

Method Of And System For Implementing A Circuit In A Device Having Programmable Logic

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US Patent:
7746099, Jun 29, 2010
Filed:
Jan 11, 2008
Appl. No.:
12/008489
Inventors:
Chi Bun Chan - San Jose CA, US
Nabeel Shirazi - San Jose CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 19/173
US Classification:
326 38, 326 8
Abstract:
A method of implementing a circuit in a device having programmable logic is disclosed. The method comprises implementing a circuit in the programmable logic of the device; storing data in a block of random access memory; performing a partial reconfiguration of the device, where new data is stored in the block of random access memory; and accessing the new data. A system of implementing a circuit in a device having programmable logic is also disclosed.

Systems And Methods Of Co-Simulation Utilizing Multiple Plds In A Boundary Scan Chain

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US Patent:
7747423, Jun 29, 2010
Filed:
Sep 27, 2006
Appl. No.:
11/527841
Inventors:
Nabeel Shirazi - San Jose CA, US
Jonathan B. Ballagh - Boulder CO, US
Chi Bun Chan - Longmont CO, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 17/50
US Classification:
703 13, 703 14
Abstract:
Systems and methods of performing co-simulation of a partitioned circuit design using multiple programmable logic devices (PLDs) coupled together to form a boundary scan chain. A host computer is coupled to the scan chain via a programming cable. Resident on the host computer are run-time co-simulation blocks corresponding to blocks from the circuit design, where each block is designated to run on one of the PLDs in the scan chain; a programming cable device driver interfacing with the programming cable; and a proxy component. The proxy component is coupled to all of the run-time co-simulation blocks and the programming cable device driver. Each co-simulation block includes a unique pattern identifier, which is also present in the associated PLD. Using this pattern identifier, data and commands targeted to a specific PLD can be extracted from the scan chain, while ignoring data and commands targeted to other PLDs in the scan chain.

Variable Clocking In Hardware Co-Simulation

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US Patent:
7937259, May 3, 2011
Filed:
Dec 18, 2007
Appl. No.:
12/002838
Inventors:
Chi Bun Chan - San Jose CA, US
Bradley L. Taylor - San Jose CA, US
Nabeel Shirazi - San Jose CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G06F 9/455
US Classification:
703 28
Abstract:
Various embodiments of a co-simulation system are disclosed. In one embodiment, a data processing arrangement executes a simulator that simulates a first block of an electronic circuit design. A first clock source generates a first clock signal, and a second clock source generates a second clock signal. The first and second clock signals are independent one from another, and an operating frequency of the second clock signal is dynamically adjustable from a clock control interface. A programmable logic device (PLD) is configured with logic that includes a co-simulation interface clocked by the first clock signal, a second block of the electronic circuit design that is clocked by the second clock signal, and a synchronizer that controls data transmission between the co-simulation interface and the second block.
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Nabeel Shirazi from Carlsbad, CA Get Report