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Mustafa Keskin

from San Diego, CA
Age ~50
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Also known as:
Mustafa Keslin, O Keskin, Mustafa N
Phone and address:
10964 Ivy Hill Dr, San Diego, CA 92131
Related to:
Baha KeskinNurcan Keskin, 49
Connected to:
Emre Keskin, 44Nihat Keskin, 59Helen E Keskinen, 100Marko Keskinen, 55Julian R Keskinyan, 52Samantha Keskool, 59Tarvo T Keskula, 68Kee A Kesl, 63Carmen R Keslar, 63Carrie L Keslar, 40

Mustafa Keskin Phones & Addresses

  • 10964 Ivy Hill Dr, San Diego, CA 92131
  • 10964 Ivy Hill Dr #5, San Diego, CA 92131
  • 11346 Merritage Ct, San Diego, CA 92131
  • 8510 Costa Verde Blvd, San Diego, CA 92122
  • Salt Lake City, UT
  • La Jolla, CA
  • Corvallis, OR

Resumes

Resumes

Mustafa Keskin Photo 1

Senior Director, Technology

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Location:
11346 Merritage Ct, San Diego, CA 92131
Industry:
Semiconductors
Work:
Qualcomm
Senior Director, Technology
Broadcom Mar 2011 - Sep 2013
Senior Principal Scientist - Ic Design
Higher Education Council Turkiye Apr 2012 - Apr 2012
Docent
Broadcom Aug 2009 - Mar 2011
Principal Scientist - Ic Design
Sequoia Communications Oct 2007 - Jul 2009
Senior Staff Design Engineer
Education:
Uc San Diego 2019 - 2020
Oregon State University 1998 - 2001
Doctorates, Doctor of Philosophy University of Southern California 1996 - 1998
Master of Science, Masters, Electrical Engineering Eskişehir Osmangazi Üniversitesi 1990 - 1994
Bachelors, Bachelor of Science, Electronics Engineering, Electronics Anadolu University
Eskişehir Osmangazi Üniversitesi
Skills:
Mixed Signal
Soc
Integrated Circuit Design
Cmos
Analog
Ic
Circuit Design
Electronics
Asic
Analog Circuit Design
Matlab
Rf
Digital Signal Processing
Vlsi
Semiconductors
Low Power Design
Integrated Circuits
Debugging
System on A Chip
Pll
Simulations
Fpga
System Development
Digital Signal Processors
Cadence Virtuoso
Application Specific Integrated Circuits
Signal Processing
Wireless
Spectre
Cadence
Electrical Engineering
Baseband
Hardware Architecture
Pcb Design
Wireless Technologies
Interests:
Analog and Digital Signal Processing
Bilginer Gulmezoglu
Ieee Journal
Dzhafarov
Circuits and Systems Ii
Speech and Audio Proc
Barkana
2012
Solid State Circuits
Esscirc
Keskin
Express Briefs
Un Ku Moon
Temes
Ieee Tran
Languages:
English
Turkish
Mustafa Keskin Photo 2

Mustafa Keskin

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Mustafa Keskin

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Publications

Us Patents

Gain Error Correction In An Analog-To-Digital Converter

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US Patent:
7161512, Jan 9, 2007
Filed:
Aug 31, 2005
Appl. No.:
11/217154
Inventors:
Mustafa Keskin - San Diego CA, US
Assignee:
Qualcomm Inc. - San Diego
International Classification:
H03M 1/12
US Classification:
341118, 341172
Abstract:
An error correction circuit for use with an analog-to-digital converter (ADC) comprising correction capacitance switching means coupled to the correction capacitance means. The switching means being coupled to ground and to a plurality of reference voltages and being arranged to a couple a bottom plate of the correction capacitance means to ground during a sample phase of the ADC and to one of a plurality of reference voltages during a hold phase of the ADC.

Delay Circuits Matching Delays Of Synchronous Circuits

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US Patent:
7940100, May 10, 2011
Filed:
Sep 24, 2007
Appl. No.:
11/860472
Inventors:
Mustafa Keskin - San Diego CA, US
Marzio Pedrali-Noy - San Diego CA, US
Assignee:
QUALCOMM, Incorporated - San Diego CA
International Classification:
H03L 7/06
US Classification:
327161, 327261
Abstract:
Delay circuits capable of providing delays closely matching propagation delays of synchronous circuits are described. In one design, an apparatus includes a synchronous circuit and a delay circuit. The synchronous circuit includes a forward path from a data input to a data output. The synchronous circuit receives input data and provides output data with a propagation delay. The delay circuit receives an input signal and provides a delayed input signal having a delay matching the propagation delay of the synchronous circuit. The delay circuit includes at least two logic gates in the forward path of the synchronous circuit. The synchronous and delay circuits may be implemented based on the same or similar circuit architecture. The delay circuit may be based on a replica of the synchronous circuit, with the replica having feedback loops broken and clock input coupled to appropriate logic value to always enable the delay circuit.

Programmable Delay Circuit With Integer And Fractional Time Resolution

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US Patent:
8120409, Feb 21, 2012
Filed:
Dec 20, 2007
Appl. No.:
11/962045
Inventors:
Mustafa Keskin - San Diego CA, US
Marzio Pedrali-Noy - San Diego CA, US
Assignee:
QUALCOMM, Incorporated - San Diego CA
International Classification:
H03H 11/26
US Classification:
327276, 327158, 327161, 327277, 327278, 327285
Abstract:
A programmable delay circuit capable of providing a delay with integer and fractional time resolution is described. In one exemplary design, an apparatus includes first and second delay circuits. The first delay circuit provides a first delay of an integer number of time units. The second delay circuit couples to the first delay circuit and provides a second delay of a fraction of one time unit. The first delay circuit may include multiple unit delay cells coupled in series. Each unit delay cell may provide a delay of one time unit when enabled. The second delay circuit may have first and second paths. The first path may provide a shorter delay when selected, and the second path may provide a longer delay when selected. The second path may be coupled to at least one dummy logic gate that provides extra loading to obtain the longer delay for the second path.

Low-Power Touch Screen Controller

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US Patent:
8259081, Sep 4, 2012
Filed:
Apr 4, 2008
Appl. No.:
12/098093
Inventors:
Mustafa Keskin - San Diego CA, US
Assignee:
Qualcomm Incorporated - San Diego CA
International Classification:
G06F 3/041
US Classification:
345173, 345174, 345204
Abstract:
While taking X-Y coordinate measurements to determine the location of a point of contact on a touch screen, a controller circuit drives the touch screen with a selectable voltage. Voltages output from the touch screen are converted by an ADC into the X-coordinate and Y-coordinate values. The ADC has a convertible input voltage range. If only a low touch screen detection resolution is required, then the voltage with which the touch screen is driven is made to be substantially less than the convertible input voltage range. Only a portion of the convertible input range is usable, but this is adequate for the application and power consumption is reduced. If a higher touch screen detection resolution is required, then the touch screen is driven with a higher voltage. Power consumption is increased, but more or all of the convertible input voltage range of the ADC is then usable.

Low-Voltage Cmos Switch With Novel Clock Boosting Scheme

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US Patent:
7268610, Sep 11, 2007
Filed:
Nov 12, 2004
Appl. No.:
10/986630
Inventors:
Mustafa Keskin - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
H03K 17/16
US Classification:
327390
Abstract:
A method and apparatus for boosting the gate voltages of a CMOS switch used in an integrated circuit designed in a sub-micron CMOS process is disclosed. The CMOS switch is coupled to Vin and Vout nodes, and contains PMOS and NMOS gates. Two boosting circuits are used to change the voltage on the PMOS and NMOS gates, respectively. The voltage at the NMOS gate is boosted from Vto (V+K×V). The voltage at the PMOS gate is decreased from Vto (V−k×V). The factor k is chosen such that Vout can be sampled through the entire range of Vin=Vto V, even where Vapproaches the sum of the absolute values of the threshold voltages of the respective PMOS and NMOS transistors.

Conductive Multi-Touch Touch Panel

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US Patent:
20100188345, Jul 29, 2010
Filed:
Aug 4, 2009
Appl. No.:
12/535647
Inventors:
Mustafa KESKIN - San Diego CA, US
Cheong KUN - Irvine CA, US
Louis Dominic OLIVEIRA - San Diego CA, US
International Classification:
G06F 3/041
US Classification:
345173
Abstract:
A conductive multi-touch touch-sensitive panel includes two intersecting but electrically isolated arrays of linear conductors which can be brought into electrical contact by touching the panel. A display element may be positioned beneath the two arrays of linear conductors to provide a touchscreen panel. A touch to a cover plate or member causes one or more linear conductors in one array to contact one or more linear conductors in the other array. The location of a touch to the panel can be detected by individually or sequentially applying an electrical signal, such as a voltage or current, to each linear conductor in one array while sensing voltage or current on each of the linear conductors in the other array.

Rail-To-Rail Delay Line For Time Analog-To-Digital Converters

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US Patent:
7106239, Sep 12, 2006
Filed:
Aug 3, 2005
Appl. No.:
11/197172
Inventors:
Mustafa Keskin - San Diego CA, US
Assignee:
Qualcomm Incorporated - San Diego CA
International Classification:
H03M 1/60
US Classification:
341157, 341155
Abstract:
A time-analog-to-digital converter (TAD) utilizes a time-to-digital approach for analog-to-digital conversion. The TAD includes two voltage-to-delay converters (VDCs), e. g. , CMOS inverter chains, in order to increase the dynamic range of the TAD. Each VDC can handle a different range of input voltages. Comparators compare the input signal voltage to reference voltages corresponding to the different ranges of input voltage and a selector selects one of the VDC line outputs based on the range in which the input signal lies. A filter estimates the input signal voltage from a delay signal from the selected output.

Robust Circuitry For Passive Fundamental Components

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US Patent:
20230098996, Mar 30, 2023
Filed:
Sep 24, 2021
Appl. No.:
17/485092
Inventors:
- San Diego CA, US
Marzio Pedrali-Noy - San Diego CA, US
Charles James Persico - Rancho Santa Fe CA, US
Mustafa Keskin - San Diego CA, US
International Classification:
G06F 11/07
G06F 13/40
Abstract:
An apparatus is disclosed for making circuitry with passive fundamental components more robust. In example implementations, an apparatus includes at least one passive fundamental component and at least one redundant passive fundamental component. The apparatus also includes fault tolerant circuitry coupled to the at least one passive fundamental component and the at least one redundant passive fundamental component. The fault tolerant circuitry includes fault detection circuitry configured to detect a fault of the at least one passive fundamental component. The fault tolerant circuitry also includes component repair circuitry configured to disconnect the at least one passive fundamental component based on the fault.
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Mustafa Keskin from San Diego, CA, age ~50 Get Report