Search

Mukul D Saran

from Richardson, TX
Age ~66
Get Report
Related to:
Dollyben J ShahSaumya Saran, 33Chirag K Shah, 38Anshu Saran, 61Aditi Saran, 37Saumya Saran, 34
Connected to:
Andrea S Saran, 57Eileen Saran, 65Harpal S Saran, 76Manvi Saran, 36Mary Saran, 100Monica Saran, 44Niti N Saran, 50Patricia A Saran, 78Sarbjit K Saran, 63Simran Saran, 30

Mukul Saran Phones & Addresses

  • 2902 Madison Ct, Richardson, TX 75082 (972) 664-1679
  • Plano, TX
  • 2902 Madison Ct, Richardson, TX 75082 (214) 374-7229

Work

Position: Service Occupations

Education

Degree: High school graduate or higher

Public records

Vehicle Records

Mukul Saran

View page
Address:
2902 Madison Ct, Richardson, TX 75082
Phone:
(972) 664-1679
VIN:
4T1BK36BX7U229037
Make:
TOYOTA
Model:
AVALON
Year:
2007

Resumes

Resumes

Mukul Saran Photo 1

Physics, Math And Sat Tutoring

View page
Location:
Dallas, TX
Industry:
Semiconductors
Work:
Texas Instruments - Dallas, TX since May 2004
Reliability Engineer, Senior Mem Tech Staff
Texas Instruments Apr 2000 - Apr 2004
ASIC Packaging Manager
Texas Instruments Nov 1995 - Apr 2000
Sr Process Engineer
NORTEL Aug 1988 - Nov 1995
Senior process development engineer
Education:
University of Manitoba 1981 - 1986
Ph.D, Physics Delhi University 1978 - 1980
M.Sc., Solid State Physics
Skills:
Semiconductors
Semiconductor Industry
Ic
Failure Analysis
Product Engineering
Cmos
Design of Experiments
Manufacturing
Reliability
Analog
Reliability Engineering
Process Simulation
Process Engineering
Reliability Test
Quality System
Root Cause Analysis
Asic
Microelectronics
Silicon
Semiconductor Process
Process Integration
Thin Films
Engineering Management
Problem Solving
Process Development
Customer Support
Business Process
Spc
Jmp
Yield
Cvd
Interests:
Education
Languages:
French
Hindi
Mukul Saran Photo 2

Mukul Saran

View page

Publications

Us Patents

Method For Reducing Via Resistance In Small High Aspect Ratio Holes Filled Using Aluminum Extrusion

View page
US Patent:
6443743, Sep 3, 2002
Filed:
Oct 5, 2000
Appl. No.:
09/679067
Inventors:
Mukul Saran - Richardson TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01R 1200
US Classification:
439 82, 439931, 174266, 174261, 174262
Abstract:
A method of forming an electrical interconnect through a via to electrically couple two electrically conductive layers and the device. There are provided a pair of electrically conductive layers and an electrically insulating layer between the pair of electrically conductive layers having a via extending between the pair of electrically conductive layers. A layer of titanium is formed covering the walls of the via and extending onto one of the pair of electrically conductive layers. A thin layer of titanium nitride with a poor step ?? technique is formed covering the titanium on the walls but not covering the titanium on the one of the pair of electrically conductive layers. The remainder of the via is filled with aluminum. The layer of titanium and the layer of titanium nitride preferably extend out of the via and between the electrically insulating layer and at least one of the pair of electrically conductive layers. The aluminum is substantially everywhere spaced from the portion of the layer of titanium covering the walls of the via.

Fine Pitch System And Method For Reinforcing Bond Pads In Semiconductor Devices

View page
US Patent:
6448650, Sep 10, 2002
Filed:
May 14, 1999
Appl. No.:
09/312385
Inventors:
Mukul Saran - Richardson TX
Charles A. Martin - Melissa TX
Ronald H. Cox - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2352
US Classification:
257758, 257750, 257763, 257786, 257773, 257774, 257775
Abstract:
A reinforcing system and method of fabrication for a semiconductor integrated circuit bond pad comprises a first dielectric layer or stack disposed under the bond pad; at least one second dielectric layer or stack disposed under the first dielectric layer; and a reinforcing metal structure disposed into the second dielectric layer such that the patterns of the metal structure and the second dielectric layer comprise a uniformly flat interface towards the first dielectric layer. The patterns of the metal structure and the second dielectric layer comprise feature sizes and fine pitches used in the integrated circuit.

High Capacitance Damascene Capacitors

View page
US Patent:
6617208, Sep 9, 2003
Filed:
Aug 17, 2001
Appl. No.:
09/932400
Inventors:
Mukul Saran - Richardson TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 48242
US Classification:
438240, 438241, 438253, 438396, 257306, 257301, 257295
Abstract:
The invention describes a high capacitance damascene capacitor. A etch-stop/capacitor dielectric layer is sandwiched between two conductive plates and to form an integrated circuit capacitor. One metal plate is copper formed using a damascene process. The high capacitance of the structure is due to the thin high k dielectric material used to form the etch-stop/capacitor dielectric layer.

System And Method For Reinforcing A Bond Pad

View page
US Patent:
6625882, Sep 30, 2003
Filed:
Feb 11, 1999
Appl. No.:
09/248303
Inventors:
Mukul Saran - Richardson TX
Charles A. Martin - McKinney TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01R 900
US Classification:
29843, 29846, 29840, 22818021, 22818022
Abstract:
A reinforcing system for a bond which includes at least one dielectric layer or stack disposed under the bond pad. A reinforcing patterned structure is disposed in the dielectric layer or stack with the delectric filling the portion of the patterned structure from which the structure was removed after patterning.

Fine Pitch System And Method For Reinforcing Bond Pads In Semiconductor Devices

View page
US Patent:
6818540, Nov 16, 2004
Filed:
Jul 23, 2002
Appl. No.:
10/201725
Inventors:
Mukul Saran - Richardson TX
Charles A. Martin - Melissa TX
Ronald H. Cox - Plano TX
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 2144
US Classification:
438612, 438622, 438623, 438637
Abstract:
A reinforcing system and method of fabrication for a semiconductor integrated circuit bond pad comprises a first dielectric layer or stack disposed under the bond pad; at least one second dielectric layer or stack disposed under the first dielectric layer; and a reinforcing metal structure disposed into the second dielectric layer such that the patterns of the metal structure and the second dielectric layer comprise a uniformly flat interface towards the first dielectric layer. The patterns of the metal structure and the second dielectric layer comprise feature sizes and fine pitches used in the integrated circuit.

Semiconductor Packages For Enhanced Number Of Terminals, Speed And Power Performance

View page
US Patent:
6873040, Mar 29, 2005
Filed:
Jul 8, 2003
Appl. No.:
10/614851
Inventors:
Gregory E. Howard - Dallas TX, US
Mukul Saran - Richardson TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L023/48
US Classification:
257691, 257693, 257775, 257787
Abstract:
An integrated circuit device package with a first part () having a cavity () to mount the chip (), further I/O terminals () on the top surface and terminals () on the bottom surface. The chip has contact pads (and ). The second part () of the package has bottom surface terminals () aligned with the chip contact pads, and bottom terminals () aligned with the terminals () of the first package part. The connections are provided by stud bumps between the chip contact pads and terminals (), and by reflow material between terminals () and (). The connector lines (and ) in the second package part () comprise signal/power and ground layers. The layers are spaced by insulation between. 10 and 50 μm thick, and the connector lines have a width less than three times the insulator thickness.

Apparatus For Improved Power Distribution In Wirebond Semiconductor Packages

View page
US Patent:
7151309, Dec 19, 2006
Filed:
Aug 27, 2004
Appl. No.:
10/928016
Inventors:
Mukul Saran - Richardson TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 23/52
US Classification:
257691, 257692, 257693
Abstract:
A semiconductor package comprising a die adjacent a substrate, a supporting plate adjacent the die, and a conducting plate abutting the supporting plate and electrically coupled to a metal apparatus adjacent the substrate and the die using a plurality of bond wires. The metal apparatus supplies power to the conducting plate.

Semiconductor Packages For Enhanced Number Of Terminals, Speed And Power Performance

View page
US Patent:
7338837, Mar 4, 2008
Filed:
Feb 7, 2005
Appl. No.:
11/053638
Inventors:
Gregory E. Howard - Dallas TX, US
Mukul Saran - Richardson TX, US
Assignee:
Texas Instruments Incorporated - Dallas TX
International Classification:
H01L 21/44
H01L 21/48
H01L 21/50
US Classification:
438109, 257686, 257777, 257E23085
Abstract:
An integrated circuit device package with a first part () having a cavity () to mount the chip (), further I/O terminals () on the top surface and terminals () on the bottom surface. The chip has contact pads (and ). The second part () of the package has bottom surface terminals () aligned with the chip contact pads, and bottom terminals () aligned with the terminals () of the first package part. The connections are provided by stud bumps between the chip contact pads and terminals (), and by reflow material between terminals () and (). The connector lines (and ) in the second package part () comprise signal/power and ground layers. The layers are spaced by insulation between 10 and 50 μm thick, and the connector lines have a width less than three times the insulator thickness.
Control profile
Mukul D Saran from Richardson, TX, age ~66 Get Report