US Patent:
20070299998, Dec 27, 2007
Inventors:
Mordechay Beck - Cupertino CA, US
Dan Kikinis - Saratoga CA, US
International Classification:
G06F 13/40
Abstract:
In a computer bus architecture, a system for improving performance in data transmitting between bussed devices includes a processor connected to the bus architecture; at least one memory device bussed to the processor; a circuit on the processor for reducing the number of bus lines required for transmitting data; and a circuit on each of the at least one memory device for reconstructing the bussed signal.