Search

Monica R Nofal

from Los Altos, CA
Age ~68
Get Report
Also known as:
Fuad Abu Nofal, Fuad A Nofal, Monica M Rosenrauch, Fuad Abu Nofal Schindele, Monica Abunofal, Fuad Abu E, Monica L
Phone and address:
866 Highlands Cir, Los Altos, CA 94024
(650) 969-4786
Related to:
Leena NofalFred RosenrauchMichel Nofal, 35Lina Nofal, 33Radhida Nofal, 58
Connected to:
Asmaa Nofal, 49Bayan N Nofal, 40Dalia Nofal, 50Fuad A Nofal, 67Manal Nofal, 45Zaid Nofal, 114Mickeila A Nofchissey, 46Heather J Noffke, 45Helena E Noffke, 34Candace D Noffs, 73

Monica Nofal Phones & Addresses

  • 866 Highlands Cir, Los Altos, CA 94024 (650) 969-4786
  • Santa Cruz, CA
  • Boston, MA
  • Watsonville, CA
  • Cupertino, CA
  • 866 Highlands Cir, Los Altos, CA 94024

Work

Company: Apple Jul 2007 Position: Director

Education

School / High School: Technion - Israel Institute of Technology

Skills

Eda • Microprocessors • Ic • Asic • Hardware Architecture • Fpga • Logic Design • Semiconductors • Cadence • Physical Design • Formal Verification • Verilog • Functional Verification • Program Management • Vlsi • Ethernet

Industries

Computer Hardware

Resumes

Resumes

Monica Nofal Photo 1

President

View page
Location:
San Francisco, CA
Industry:
Computer Hardware
Work:
Apple
Director
Nova Semiconductors
President
Sgi May 1991 - Oct 1998
Mts and Verification Manager
Intel Corporation Nov 1983 - May 1991
Mts and Technical Lead
Education:
Technion - Israel Institute of Technology
Skills:
Eda
Microprocessors
Ic
Asic
Hardware Architecture
Fpga
Logic Design
Semiconductors
Cadence
Physical Design
Formal Verification
Verilog
Functional Verification
Program Management
Vlsi
Ethernet

Publications

Us Patents

Loading Previously Dispatched Slots In Multiple Instruction Dispatch Buffer Before Dispatching Remaining Slots For Parallel Execution

View page
US Patent:
6691221, Feb 10, 2004
Filed:
May 24, 2001
Appl. No.:
09/863898
Inventors:
Chandra Joshi - Saratoga CA
Paul Rodman - Palo Alto CA
Peter Hsu - Fremont CA
Monica R. Nofal - Los Altos CA
Assignee:
Mips Technologies, Inc. - Mountain View CA
Kabushiki Kaisha Toshiba - Tokyo
International Classification:
G06F 938
US Classification:
712215, 712 23, 712206
Abstract:
A computing system has first and second instruction storing circuits, each instruction storing circuit storing N instructions for parallel output. An instruction dispatch circuit, coupled to the first instruction storing circuit dispatches L instructions stored in the first instruction storing circuit, wherein L is less than or equal to N. An instruction loading circuit, coupled to the instruction dispatch circuit and to the first and second instruction storing circuits, loads L instructions from the second instruction storing circuit into the first instruction storing circuit after the L instructions are dispatched from the first instruction storing circuit and before further instructions are dispatched from the first instruction storing circuit. The instruction loading circuit loads the L instructions from the second instruction storing circuit into the positions previously occupied by the L instructions dispatched from the first instruction storing circuit. A feedback path is also provided to reload an instruction not previously dispatched.

Branch Prediction Entry With Target Line Index Calculated Using Relative Position Of Second Operation Of Two Step Branch Operation In A Line Of Instructions

View page
US Patent:
62471244, Jun 12, 2001
Filed:
Jul 30, 1999
Appl. No.:
9/363635
Inventors:
Chandra Joshi - Saratoga CA
Paul Rodman - Palo Alto CA
Peter Hsu - Fremont CA
Monica R. Nofal - Los Altos CA
Assignee:
MIPS Technologies, Inc. - Mountain View CA
International Classification:
G06F 932
US Classification:
712240
Abstract:
A computing system contains an apparatus having an instruction memory to store a plurality of lines of a plurality of instructions, and a branch memory to store a plurality of branch prediction entries, each branch prediction entry containing information for predicting whether a branch designated by a branch instruction stored in the instruction memory will be taken when the branch instruction is executed. Each branch prediction entry includes a branch target field for indicating a target address of a line containing a target instruction to be executed if the branch is taken, a destination field indicating where the target instruction is located within the line indicated by the branch target address, and a source field indicating where the branch instruction is located within the line corresponding to the target address. A counter stores an address value used for addressing the instruction memory, and an incrementing circuit increments the address value in the counter for sequentially addressing the lines in the instruction memory during normal sequential operation. A counter loading circuit loads the target address into the counter when the branch prediction entry predicts the branch designated by the branch instruction stored in the instruction memory will be taken when the branch instruction is executed, causing the line containing the target instruction to be fetched and entered into the pipeline immediately after the line containing the branch instruction.

Debug Mode For A Superscalar Risc Processor

View page
US Patent:
55375383, Jul 16, 1996
Filed:
Dec 15, 1993
Appl. No.:
8/166969
Inventors:
Joseph P. Bratt - San Jose CA
John Brennan - Mountain View CA
Peter Y. Hsu - Fremont CA
Chandra S. Joshi - Saratoga CA
William A. Huffman - Los Gatos CA
Monica R. Nofal - Los Altos CA
Paul Rodman - Palo Alto CA
Joseph T. Scanlon - Sunnyvale CA
Man K. Tang - Milpitas CA
Assignee:
Silicon Graphics, Inc. - Mountain View CA
International Classification:
G06F 1134
G06F 930
US Classification:
39518314
Abstract:
A processor system that is switchable between a normal mode of operation without precise floating point exceptions and a debug mode of operation with precise floating point exceptions. The processor system includes a dispatch for dispatching integer and floating point instructions, an integer unit having a multi-stage integer pipeline for executing the integer instructions, and a floating point unit having a multi-stage floating point pipeline for executing the floating point instructions. The system begins operation in the normal mode, and upon receipt of an instruction to "switch to debug mode," the processor switches to the debug mode of operation with precise exceptions. In the debug mode, once a floating point instruction has been dispatched, all other instructions are prevented from being committed until the system determines whether the floating point instruction generates an exception. Thus, permitting the system to signal precise exceptions when not in the normal mode.

Apparatus For Processing Instructions In A Computing System

View page
US Patent:
56049099, Feb 18, 1997
Filed:
Dec 15, 1993
Appl. No.:
8/168744
Inventors:
Chandra Joshi - Saratoga CA
Paul Rodman - Palo Alto CA
Peter Hsu - Fremont CA
Monica R. Nofal - Los Altos CA
Assignee:
Silicon Graphics Computer Systems, Inc. - Mountain View CA
International Classification:
G06F 900
US Classification:
395384
Abstract:
A computing system has first and second instruction storing circuits, each instruction storing circuit storing N instructions for parallel output. An instruction dispatch circuit, coupled to the first instruction storing circuit dispatches L instructions stored in the first instruction storing circuit, wherein L is less than or equal to N. An instruction loading circuit, coupled to the instruction dispatch circuit and to the first and second instruction storing circuits, loads L instructions from the second instruction storing circuit into the first instruction storing circuit after the L instructions are dispatched from the first instruction storing circuit and before further instructions are dispatched from the first instruction storing circuit. A bypass circuit for bypassing the second instruction storing circuit is also provided.

Invalidating Instructions In Fetched Instruction Blocks Upon Predicted Two-Step Branch Operations With Second Operation Relative Target Address

View page
US Patent:
59548150, Sep 21, 1999
Filed:
Jan 10, 1997
Appl. No.:
8/781851
Inventors:
Chandra Joshi - Saratoga CA
Paul Rodman - Palo Alto CA
Peter Hsu - Fremont CA
Monica R. Nofal - Los Altos CA
Assignee:
Silicon Graphics, Inc. - Mountain View CA
International Classification:
G06F 938
US Classification:
712237
Abstract:
A computing system that contains an apparatus comprising an instruction memory to store a plurality of lines of a plurality of instructions, and a branch memory to store a plurality of branch prediction entries, each branch prediction entry containing information for predicting whether a branch designated by a branch instruction stored in the instruction memory will be taken when the branch instruction is executed. Each branch prediction entry includes a branch target field for indicating a target address of a line containing a target instruction to be executed if the branch is taken, a destination field indicating where the target instruction is located within the line indicated by the branch target address, and a source field indicating where the branch instruction is located within the line corresponding to the target address. A counter stores an address value used for addressing the instruction memory, and an incrementing circuit increments the address value in the counter for sequentially addressing the lines in the instruction memory during normal sequential operation. A counter loading circuit loads the target address into the counter when the branch prediction entry predicts the branch designated by the branch instruction stored in the instruction memory will be taken when the branch instruction is executed, causing the line containing the target instruction to be fetched and entered into the pipeline immediately after the line containing the branch instruction.
Control profile
Monica R Nofal from Los Altos, CA, age ~68 Get Report