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Mohan Rajagopalan

from Mountain View, CA
Age ~46
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Also known as:
Mohan Rajgopalan, Mohan N
Phone and address:
321 Sleeper Ave, Mountain View, CA 94040
Related to:
Aruna RajagopalanRajagopala Rajagopalan VenkatarRavi Rajagopalan
Connected to:
Aparna Rajagopal, 51Dheeraj Rajagopal, 34Geethalakshmi Rajagopalan, 62Gopal Rajagopalan, 87Janaki K Rajagopal, 67Jayalakshmi Rajagopal, 78Kasturi R Rajagopalan, 37Mathangi Rajagopal, 56Mukunda G Rajagopala, 59Nisha Rajagopalan, 42

Mohan Rajagopalan Phones & Addresses

  • 321 Sleeper Ave, Mountain View, CA 94040
  • Sunnyvale, CA
  • Tucson, AZ

Work

Company: Criteo Jul 2011 Position: Business development manager

Education

School / High School: Georgetown University - The McDonough School of Business Jan 2009 Specialities: MBA in Corporate Strategy, Marketing, Online Marketing

Skills

Business Case • Marketing Strategy • Online Marketing • SEM • Product Management • Web Project Management • Modeling • Market Analysis • Business Analysis • Business Strategy • Online Advertising • Business Operations Management • Identifying New Business Opportunities • Financial Modeling • Pricing Strategy • New Business Development • M&A experience • Digital Marketing • Data Analysis • Management Consulting • Project Management • Client and Partner Relationship Management • Business Model Design • Business Case Development • Product Development • Corporate Strategy • Strategic Roadmap Development • Market & Business Analysis • comScore: Ad Metrix and Plan Metrix • Online Marketing Strategy • New Media Strategy • Omniture • Negotiations • Digital Strategy • E-Commerce • Online Advertising • Business Operations (Growth and Reengine... • Financial Modeling • Pricing Strategy

Resumes

Resumes

Mohan Rajagopalan Photo 1

Frequent Flying, Problem Solving, Slide Aggregating, Team Shepherding,Loyalty Points Collector

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Position:
Engagement Manager at McKinsey & Company
Location:
Mountain View, California
Industry:
Management Consulting
Work:
McKinsey & Company since Apr 2011
Engagement Manager
Intel Feb 2006 - Apr 2011
Staff Research Scientist
Sun Microsystems May 2000 - Aug 2000
Intern
Education:
University of Arizona 2001 - 2006
University of Arizona 1999 - 2001
University of Mumbai 1995 - 1999
Skills:
Distributed Systems
Architecture
Compilers
Programming Languages
Operating Systems
Hardware
Algorithms
Analytics
Strategy
Pricing
Big Data
Organizational Structure
Interests:
New technology, exploratory research in systems design and optimization, innovation, productization of research and bringing technology to the market.
Honor & Awards:
•8+ departmental and divison level awards at Intel Labs. • William C. Carter dissertation award, IEEE/IFIP Dependable Systems and Networks, June 2005. • IFIP/ACM Middleware 2001 Best Paper Award, June 2001 Departmental Graduate Fellowship, Spring 2001 • 8+ Patents
Mohan Rajagopalan Photo 2

Senior Director Of Product Management, Ai And Ml

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Location:
321 Sleeper Ave, Mountain View, CA 94040
Industry:
Computer Software
Work:
Splunk
Senior Director of Product Management, Ai and Ml
Xcalar, Inc. Jan 2018 - May 2018
Vice President Engineering and Products
Akoonu 2017 - 2018
Advisor
Misc Startups 2017 - 2018
Advisor and Advisory Board Member
Yaap.io 2013 - 2017
Chief Executive Officer
Education:
University of Arizona 2001 - 2006
Doctorates, Doctor of Philosophy University of Arizona 1999 - 2001
Master of Science, Masters University of Mumbai 1995 - 1999
Skills:
Distributed Systems
Architecture
Compilers
Programming Languages
Operating Systems
Hardware
Algorithms
Analytics
Strategy
Pricing
Big Data
Organizational Structure
Architectures
Start Ups
C
Product Management
Integration
Business Strategy
Management
C++
Software Development
Interests:
Innovation
New Technology
Languages:
English
Mohan Rajagopalan Photo 3

Mohan Rajagopalan San Francisco Bay Area, CA

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Work:
Criteo

Jul 2011 to Present
Business Development Manager
The Huffington Post

Jan 2011 to Apr 2011
MBA Marketing Externship
Rosetta Stone

Jun 2010 to Aug 2010
Online Marketing Intern
The Huffington Post

Jan 2010 to Mar 2010
Marketing Consultant
Accenture

Jan 2005 to Sep 2009
Management Consultant
Education:
Georgetown University - The McDonough School of Business
Jan 2009 to Jan 2011
MBA in Corporate Strategy, Marketing, Online Marketing
The University of Texas at Austin
Jan 2001 to Jan 2005
B.A in Government
Skills:
Business Case, Marketing Strategy, Online Marketing, SEM, Product Management, Web Project Management, Modeling, Market Analysis, Business Analysis, Business Strategy, Online Advertising, Business Operations Management, Identifying New Business Opportunities, Financial Modeling, Pricing Strategy, New Business Development, M&A experience, Digital Marketing, Data Analysis, Management Consulting, Project Management, Client and Partner Relationship Management, Business Model Design, Business Case Development, Product Development, Corporate Strategy, Strategic Roadmap Development, Market & Business Analysis, comScore: Ad Metrix and Plan Metrix, Online Marketing Strategy, New Media Strategy, Omniture, Negotiations, Digital Strategy, E-Commerce, Online Advertising, Business Operations (Growth and Reengineering), Financial Modeling, Pricing Strategy

Business Records

Name / Title
Company / Classification
Phones & Addresses
Mohan Rajagopalan
President
Yaap Up, Inc
Courier Service
321 Sleeper Ave, Mountain View, CA 94040

Publications

Us Patents

Method And Apparatus For Supporting Scalable Coherence On Many-Core Products Through Restricted Exposure

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US Patent:
7984244, Jul 19, 2011
Filed:
Dec 28, 2007
Appl. No.:
12/005785
Inventors:
Joshua B. Fryman - Sunnyvale CA, US
Mohan Rajagopalan - Mountain View CA, US
Anwar Ghuloum - Menlo Park CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/00
US Classification:
711141, 711163, 711E12069
Abstract:
In one embodiment, a multi-core processor having cores each associated with a cache memory, can operate such that when a first core is to access data owned by a second core present in a cache line associated with the second core, responsive to a request from the first core, cache coherency state information associated with the cache line is not updated. A coherence engine associated with the processor may receive the data access request and determine that the data is of a memory page owned by the first core and convert the data access request to a non-cache coherent request. Other embodiments are described and claimed.

Future Scheduling By Direct Representation Of Possible Dependencies

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US Patent:
8225326, Jul 17, 2012
Filed:
Mar 17, 2008
Appl. No.:
12/049914
Inventors:
Leaf Petersen - Seattle WA, US
Anwar Ghuloum - Menlo Park CA, US
Mohan Rajagopalan - Mountain View CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/46
G06F 9/52
US Classification:
718106, 718102, 718104, 718105
Abstract:
A method for evaluating objects in a data structure is provided. The method includes assigning one or more objects to one or more nodes in a data structure having at least a root node, in which the objects are assigned to the nodes in accordance with a first order to maintain pre-existing dependencies between the objects and to allow the objects to be evaluated in a serial manner to avoid deadlock when concurrently executing threads to evaluate the objects, and selecting a first object for evaluation, in response to determining that the current object is unevaluated.

Method And Apparatus For Supporting Scalable Coherence On Many-Core Products Through Restricted Exposure

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US Patent:
8312225, Nov 13, 2012
Filed:
Jun 9, 2011
Appl. No.:
13/156777
Inventors:
Joshua B. Fryman - Sunnyvale CA, US
Mohan Rajagopalan - Mountain View CA, US
Anwar Ghuloum - Menlo Park CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 12/00
US Classification:
711141, 711163, 711E12069
Abstract:
In one embodiment, a multi-core processor having cores each associated with a cache memory, can operate such that when a first core is to access data owned by a second core present in a cache line associated with the second core, responsive to a request from the first core, cache coherency state information associated with the cache line is not updated. A coherence engine associated with the processor may receive the data access request and determine that the data is of a memory page owned by the first core and convert the data access request to a non-cache coherent request. Other embodiments are described and claimed.

Language Level Support For Shared Virtual Memory

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US Patent:
8397241, Mar 12, 2013
Filed:
Dec 30, 2008
Appl. No.:
12/317854
Inventors:
Zhou Xiaocheng - Beijing, CN
Shoumeng Yan - Beijing, CN
Ying Gao - Beijing, CN
Hu Chen - Beijing, CN
Peinan Zhang - Beijing, CN
Mohan Rajagopalan - Mountain View CA, US
Avi Mendelson - Haifa, IL
Bratin Saha - Santa Clara CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/44
G06F 13/14
G06F 13/00
US Classification:
719312, 719328, 719330, 345520, 711147
Abstract:
Embodiments of the invention provide language support for CPU-GPU platforms. In one embodiment, code can be flexibly executed on both the CPU and GPU. CPU code can offload a kernel to the GPU. That kernel may in turn call preexisting libraries on the CPU, or make other calls into CPU functions. This allows an application to be built without requiring the entire call chain to be recompiled. Additionally, in one embodiment data may be shared seamlessly between CPU and GPU. This includes sharing objects that may have virtual functions. Embodiments thus ensure the right virtual function gets invoked on the CPU or the GPU if a virtual function is called by either the CPU or GPU.

Shared Virtual Memory

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US Patent:
8531471, Sep 10, 2013
Filed:
Dec 30, 2008
Appl. No.:
12/317853
Inventors:
Hu Chen - Beijing, CN
Ying Gao - Beijing, CN
Zhou Xiaocheng - Beijing, CN
Shoumeng Yan - Beijing, CN
Peinan Zhang - Beijing, CN
Mohan Rajagopalan - Mountain View CA, US
Jesse Fang - San Jose CA, US
Avi Mendelson - Haifa, IL
Bratin Saha - Santa Clara CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 15/167
G06F 12/00
G06F 12/02
G06F 12/10
US Classification:
345542, 345541, 345543, 345544, 345564, 345565, 345566, 345568
Abstract:
Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.

Concurrent Management Of Adaptive Programs

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US Patent:
8627301, Jan 7, 2014
Filed:
May 18, 2007
Appl. No.:
11/750441
Inventors:
Matthew Hammer - Stoughton WI, US
Mohan Rajagopalan - Mountain View CA, US
Anwar Ghuloum - Menlo Park CA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 9/44
G06F 9/45
US Classification:
717158, 717132, 717128, 717130, 717131, 717149, 717156
Abstract:
A method for concurrent management of adaptive programs is disclosed wherein changes in a set of modifiable references are initially identified. A list of uses of the changed references is next computed using records made in structures of the references. The list is next inserted into an elimination queue. Comparison is next made of each of the uses to the other uses to determine independence or dependence thereon. Determined dependent uses are eliminated and the preceding steps are repeated for all determined independent uses until all dependencies have been eliminated.

Non-Blocking Wait-Free Data-Parallel Scheduler

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US Patent:
20120159495, Jun 21, 2012
Filed:
Dec 17, 2010
Appl. No.:
12/971891
Inventors:
Mohan Rajagopalan - Mountain View CA, US
Ali-Reza Adl-Tabatabai - San Jose CA, US
Yang Ni - Sunnyvale CA, US
Adam Welc - San Francisco CA, US
Richard L. Hudson - Florence MA, US
International Classification:
G06F 9/46
US Classification:
718102
Abstract:
Methods, systems, and mediums are described for scheduling data parallel tasks onto multiple thread execution units of processing system. Embodiments of a lock-free queue structure and methods of operation are described to implement a method for scheduling fine-grained data-parallel tasks for execution in a computing system. The work of one of a plurality of worker threads is wait-free with respect to the other worker threads. Each node of the queue holds a reference to a task that may be concurrently performed by multiple thread execution units, but each on a different subset of data. Various embodiments relate to software-based scheduling of data-parallel tasks on a multi-threaded computing platform that does not perform such scheduling in hardware. Other embodiments are also described and claimed.

Two Way Communication Support For Heterogenous Processors Of A Computer Platform

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US Patent:
20130061240, Mar 7, 2013
Filed:
Oct 30, 2009
Appl. No.:
13/504972
Inventors:
Shoumeng Yan - Beijing, CN
Xiaocheng Zhou - Beijing, CN
Ying Gao - Beijing, CN
Mohan Rajagopalan - Mountain View CA, US
Rajiv Deodhar - Phoenix AZ, US
David Putzolu - Hillsboro OR, US
Clark Nelson - Hillsboro OR, US
Milind Girkar - Sunnyvale CA, US
Robert Geva - Cupertino CA, US
Tiger Chen - Beijing, CN
Sai Luo - Beijing, CN
Stephen Junkins - Bend OR, US
Bratin Saha - Santa Clara CA, US
Ravi Narayanaswamy - San Jose CA, US
Patrick Xi - Shanghai, CN
International Classification:
G06F 13/00
US Classification:
719312
Abstract:
A computer system may comprise a computer platform and input-output devices. The computer platform may include a plurality of heterogeneous processors comprising a central processing unit (CPU) and a graphics processing unit) GPU, for example. The GPU may be coupled to a GPU compiler and a GPU linker/loader and the CPU may be coupled to a CPU compiler and a CPU linker/loader. The user may create a shared object in an object oriented language and the shared object may include virtual functions. The shared object may be fine grain partitioned between the heterogeneous processors. The GPU compiler may allocate the shared object to the CPU and may create a first and a second enabling path to allow the GPU to invoke virtual functions of the shared object. Thus, the shared object that may include virtual functions may be shared seamlessly between the CPU and the GPU.
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Mohan Rajagopalan from Mountain View, CA, age ~46 Get Report