Mitchell Grant Poplack

7356455, Apr 8, 2008

Oct 28, 2004

10/975676

Barton Quayle - San Jose CA, US
Mitchell G. Poplack - Mountain View CA, US

Quickturn Design Systems, Inc. - San Jose CA

G06F 9/455
G06F 17/50
G06G 7/62
G06F 11/00

703 23, 703 28, 703 13, 703 14, 703 24, 703 25, 703 26, 703 27, 714 30, 714 34

An optimized interface for simulation and visualization data transfer between an emulation system and simulator is disclosed. In one embodiment, a method of transferring data between a simulator to an emulator across an interface, comprises updating a simulator buffer of the simulator to contain a desired input state for an emulation cycle. A target write to the interface is performed to indicate that the emulation cycle can proceed. The emulation cycle is completed using an instruction sequencer within the interface independent of the simulator.

7440866, Oct 21, 2008

May 31, 2005

11/140722

John A. Maher - San Jose CA, US
Mitchell Grant Poplack - San Jose CA, US

Quickturn Design Systems Inc. - San Jose CA

G06F 19/00
G01R 27/28
G01R 31/00
G01R 31/14

702120, 714 33, 714 37, 703 25, 703 27

A target interface system for interfacing selected components of a communication system and methods for manufacturing and using same. Being reconfigurable to support an extensive range of conventional input/output technologies, the target interface system downloads a selected image associated with a desired input/output technology prior to runtime. The selected image identifies an appropriate output driver supply voltage, and any auxiliary voltages are controlled as functions of the output driver supply voltage to limit voltage inconsistencies. Defaulting each voltage to its least dangerous state when unprogrammed, the target interface system subsequently monitors the voltages, disabling the input/output connections if a problem is detected. The target interface system likewise detects when a selected system component is absent, unpowered, and/or wrongly powered and provides contention detection. Thereby, the target interface system can facilitate communication among the system components while inhibiting damage to the target interface system and/or the system components.

7555423, Jun 30, 2009

Dec 29, 2005

11/321201

William F. Beausoleil - Hopewell Jct NY, US
Mitchell G. Poplack - San Jose CA, US
Steven T Comfort - Poughkeepsie NY, US
Beshara Elmufdi - Sunnyvale CA, US

Quickturn Design Systems, Inc. - San Jose CA

G06F 9/455
G06F 9/45

703 23, 703 28, 716 5

The present system and methods are directed to the interconnection of clusters of emulation processors comprising emulation processors in a software-driven hardware design verification system. The processors each output one NBO output signal. The clusters are interconnected by partitioning a common NBO bus into a number of smaller NBO busses, each carrying unique NBO signals but together carrying every NBO. Each of the smaller NBO busses are passed into a series of multiplexers, each dedicated to a particular processor. The multiplexers select a signal for output back to the emulation clusters. The multiplexers that handle these smaller NBO busses are narrower than was previously required, thus reducing the amount of power, interconnect, and area required by the multiplexer array and dedicated interconnect.

7606697, Oct 20, 2009

May 31, 2005

11/141141

Mitchell G. Poplack - San Jose CA, US
John A. Maher - San Jose CA, US

Quickturn Design Systems, Inc. - San Jose CA

G06F 9/455
G06F 19/00

703 25, 375214, 702126

A signal conversion system for interfacing selected components of a communication system and methods for manufacturing and using same. The signal conversion system converts selected logic signals from one system component into a pair of differential logic signals and provides the pair of differential logic signals to a second system component, resolving any logical and/or temporal artifacts. While one or more of the selected logic signals change signal state, the signal conversion system maintains the pair of differential logic signals in a first valid combined signal state until the signal state of the selected logic signals corresponds to a second valid combined signal state for the pair of differential logic signals. The signal verification system then updates the pair of differential logic signals to have the second valid combined signal state. The system components thereby can communicate, exchanging differential communication signals while maintaining duty cycle and avoiding signaling glitches.

7606698, Oct 20, 2009

Sep 26, 2006

11/526967

Beshara G. Elmufdi - Sunnyvale CA, US
Mitchell G. Poplack - San Jose CA, US

Cadence Design Systems, Inc. - San Jose CA

G06F 9/455

703 25, 703 15, 717134, 717138, 717141, 717149

A method and apparatus for sharing data between processors within first and second discrete clusters of processors. The method comprises supplying a first amount of data from a first data array in a first discrete cluster of processors to selector logic. A second amount of data from a second data array in a second discrete cluster of processors is also supplied to the selector logic. The first or second amount of data is then selected using the selector logic, and supplied to a shared input port on a processor in the first discrete cluster of processors. The apparatus comprises selector logic for selecting between input data supplied by a first data array and a second data array. The data arrays are located within different discrete clusters of processors. The selected data is then supplied to a shared input port on a processor.

7640155, Dec 29, 2009

May 31, 2005

11/141599

Mitchell G. Poplack - San Jose CA, US
John A. Maher - San Jose CA, US

QuickTurn Design Systems, Inc. - San Jose CA

G06F 17/50
G06F 9/455
G06F 12/00
G06F 15/76
G06F 11/00
G06F 9/45

703 23, 703 13, 703 24, 703 28, 711122, 712 2, 712 10, 712 20, 712 22, 712 39, 714 28, 714735, 716 4, 716 5, 716 16, 716 17

A target interface system for interfacing selected components of a communication system and methods for manufacturing and using same. The target interface system includes target interface logic that is distributed among a plurality of reconfigurable logic devices. Being coupled via a serial link, the reconfigurable logic devices each have an input connection for receiving incoming data packets and an output connection for providing outgoing data packets. The serial link couples the input and output connections of successive reconfigurable logic devices to form a dataring structure for distributing the data packets among the reconfigurable logic devices. Thereby, the dataring structure maintains data synchronization among the reconfigurable logic devices such that the distribution of the target interface logic among the reconfigurable logic devices is transparent to software.

7721036, May 18, 2010

May 31, 2005

11/140714

Mitchell G. Poplack - San Jose CA, US
John A. Maher - San Jose CA, US

Quickturn Design Systems Inc. - San Jose CA

G06F 13/14
G06F 13/36
G06F 13/00
G06F 9/455

710305, 710 31, 710306, 703 25

A target interface system for flexibly routing and timing communication signals exchanged between selected components of a communication system and methods for manufacturing and using same. Under the control of a host system, the target interface system samples an output data signal provided by the host system and includes a reconfigurable datapath for flexibly routing the sampled data signal to a selected target I/O pin of the target interface system. The selected target I/O pin provides the sampled data signal as an outgoing target data signal to a target system and likewise receives an incoming target data signal from the target system. Upon sampling the incoming target data signal, the target interface system flexibly routes the sampled data signal to the host system as an input data signal. The target interface system thereby facilitates exchanges of communication signals between the host system and the target system.

7738398, Jun 15, 2010

Nov 17, 2004

10/992165

Barton L. Quayle - San Jose CA, US
Mitchell G. Poplack - Mountain View CA, US
Peter Tannenbaum - Highland NY, US

Quickturn Design Systems, Inc. - San Jose CA

H04L 12/28

370254

An identification system for identifying and validating selected components of a communication system and methods for manufacturing and using same. The communication system includes a host system that is configured to couple with one or more target systems. When the host system is coupled with a selected target system, the communication system can enter an identification mode wherein the selected target system can provide identification data to the host system. The identification data includes information regarding at least one target system characteristic associated with the selected target system such that the host system can attempt to identify the selected target system based at least in part upon the target system characteristics. Once the selected target system has been identified, the communication system likewise can at least partially reconfigure the host system, as necessary, such that the host system can be compatible with the selected target system.