Misbahul He Azam

6730606, May 4, 2004

Nov 3, 2000

09/705274

Misbahul Azam - Gilbert AZ
Jeffrey Pearse - Chandler AZ
Christopher J. Gass - Tempe AZ

Semiconductor Components Industries, L.L.C. - Phoenix AZ

H01L 21311

438700, 438701, 438713, 438717

A masking material ( ) is formed on a foundation layer ( ) and a substrate ( ). A mask ( ) is disposed onto the masking material ( ) where a trench ( ) is desired to be formed. An etch step removes all of the masking material ( ) except at regions where the mask ( ) was formed leaving a protruding portion ( ) with an opening ( ) on either side. An epi layer ( ), is grown on the foundation layer ( ) adjacent to the protruding portion ( ) in the opening ( ). A wet oxide etch process is used to remove the protruding portion ( ) leaving a trench ( ) formed in the epi layer ( ). To complete the process, a silicon wet etch process is used to round off the corners at an edge ( ) of the trench ( ).

6753228, Jun 22, 2004

Oct 15, 2002

10/270419

Misbahul Azam - Gilbert AZ
Jeffrey Pearse - Chandler AZ
Daniel G. Hannoun - Chandler AZ

Semiconductor Components Industries, L.L.C. - Phoenix AZ

H01L 218242

438270, 438272

A transistor ( ) is formed with a low resistance trench structure that is utilized for a gate ( ) of the transistor. The low resistance trench structure facilitates forming a shallow source region ( ) that reduces the gate-to-source capacitance.

6809396, Oct 26, 2004

Nov 25, 2002

10/303168

Peter J. Zdebel - Austin TX
Misbahul Azam - Gilbert AZ
Gary H. Loechelt - Tempe AZ
James R. Morgan - Chandler AZ
Julio C. Costa - Greensboro NC

Semiconductor Components Industries, L.L.C. - Phoenix AZ

H01L 2973

257511, 257555, 257593

An integrated circuit ( ) includes high performance complementary bipolar NPN and PNP vertical transistors ( ). The NPN transistor is formed on a semiconductor substrate whose surface ( ) is doped to form a PNP base region ( ). A film ( ) is formed on the surface with an opening ( ) over an edge of the base region. A first conductive spacer ( ) is formed along a first sidewall ( ) of the opening to define a PNP emitter region ( ) within the base region. A second conductive spacer ( ) is formed along a second sidewall ( ) of the opening to define a PNP collector region ( ).

20020121663, Sep 5, 2002

Mar 5, 2001

09/798546

Misbahul Azam - Gilbert AZ, US
Maureen Grimaldi - Chandler AZ, US
Jeffrey Pearse - Chandler AZ, US

Semiconductor Components Industries, LLC

H01L021/336
H01L029/76
H01L029/94
H01L031/062
H01L031/062
H01L031/113
H01L031/119

257/330000, 438/259000

A semiconductor device () has a substrate () having a first surface () with a

20030077869, Apr 24, 2003

Oct 18, 2001

09/982392

Keith Kamekona - Scottsdale AZ, US
James Morgan - Chandler AZ, US
Guy Averett - Mesa AZ, US
Misbahul Azam - Gilbert AZ, US
Weizhong Cai - Scottsdale AZ, US

Semiconductor Components Industries, LLC.

H01L021/331
H01L021/8222

438/309000

A method of forming a semiconductor device () includes the step of exposing a first region () of a semiconductor substrate () with a photomask (). A material is implanted into the first region to form a compound that masks the first region of the semiconductor substrate to form an electrode () of the semiconductor device.

20040219752, Nov 4, 2004

May 11, 2004

10/843639

Misbahul Azam - Gilbert AZ, US
Jeffrey Pearse - Chandler AZ, US
Daniel Hannoun - Chandler AZ, US

H01L021/336

438/270000

A transistor () is formed with a low resistance trench structure that is utilized for a gate () of the transistor. The low resistance trench structure facilitates forming a shallow source region () that reduces the gate-to-source capacitance.

6664574, Dec 16, 2003

Sep 5, 2001

09/945683

Misbahul Azam - Gilbert AZ
Gary Loechelt - Tempe AZ
Julio Costa - Phoenix AZ

Semiconductor Components Industries LLC - Phoenix AZ

H01L 310328

257197, 257198, 257616, 257586

A semiconductor component ( ) includes a semiconductor substrate ( ) that is formed with trench ( ). A semiconductor layer ( ) is formed in the trench for coupling a control signal (V ) through a sidewall ( ) of the trench to route a current (I ) through a bottom surface ( ) of the trench.