Mikhail N Bershteyn

6377912, Apr 23, 2002

Aug 13, 1999

09/374444

Stephen P. Sample - Saratoga CA
Mikhail Bershteyn - Campbell CA
Michael R. Butts - Portland CA
Jerry R. Bauer - Cupertino CA

Quickturn Design Systems, Inc. - San Jose CA

G06F 9455

703 28, 716 1

A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

6732068, May 4, 2004

Aug 2, 2001

09/922113

Stephen P. Sample - Saratoga CA
Mikhail Bershteyn - Campbell CA
Michael R. Butts - Portland OR
Jerry R. Bauer - Cupertino CA

Quickturn Design Systems Inc. - San Jose CA

G06F 9455

703 24, 703 23, 703 25, 703 27, 703 28, 326 40, 712 14, 712 15

A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

7739097, Jun 15, 2010

Apr 22, 2002

10/128178

Stephen P. Sample - Saratoga CA, US
Mikhail Bershteyn - Campbell CA, US
Michael R. Butts - Portland OR, US
Jerry R. Bauer - Cupertino CA, US

Quickturn Design Systems Inc. - San Jose CA

G06F 17/50
H04J 99/00
G06F 9/455

703 19, 703 23, 703 24, 370546, 370916

A hardware emulation system is disclosed which reduces hardware cost by time multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The hardware emulation system comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces through the use of multiplexing.

7908465, Mar 15, 2011

Nov 17, 2006

11/601235

Mitchell G. Poplack - San Jose CA, US
Mikhail Bershteyn - Cupertino CA, US

Cadence Design Systems, Inc. - San Jose CA

G06F 7/38
G06F 9/00
G06F 9/44
G06F 15/00

712227

A method and apparatus for emulating a hardware design comprising an instruction execution unit for executing at least one instruction, a memory for providing data to the instruction execution unit for processing into an output bit, and a write enable logic for controlling writing the output bit from the instruction execution unit to the memory. In this manner, the output bit produced by the instruction execution unit executing an instruction may be selectably stored in memory to facilitate efficient processing of conditional emulation operations.

8027828, Sep 27, 2011

May 31, 2006

11/444032

Mikhail Bershteyn - Cupertino CA, US
Charles Berghorn - Pleasant Valley NY, US
Mitchell G. Poplack - San Jose CA, US

Cadence Design Systems, Inc. - San Jose CA

G06F 9/455

703 23

A method, apparatus and method for compiling a hardware design for performing hardware emulation using synchronized processors is described. The apparatus comprises a plurality of processors defining a processor group for evaluating data regarding a hardware design and a synchronizer for synchronizing the operation of the processor group while emulating at least a portion of the hardware design. The method comprises providing a synchronization signal to a plurality of processors defining a processor group for evaluating data regarding a hardware design, receiving a ready signal from the processor group, and providing an execution signal to the processor group, where the execution signal causes the processor group to evaluate a submodel. The method for compiling the hardware design comprises converting at least one high-level construct into a sequence of operations and identifying a sequence of operations that comprise at least one conditional submodel.

8468009, Jun 18, 2013

Sep 28, 2006

11/541285

Mikhail Bershteyn - Cupertino CA, US
Beshara G. Elmufdi - Sunnyvale CA, US

Cadence Design Systems, Inc. - San Jose CA

G06F 9/445
G06F 9/45

703 24, 703 23

A hardware emulator having an emulation unit with a shadow processor is described. The shadow processor is capable of performing an extra look up table (LUT) operation in addition to the LUT operation performed by a processor within the emulation unit. The emulation unit comprises a memory for supplying a first amount of data to a shadow processor register, wherein the shadow processor register stores the first amount of data for later retrieval. The data stored in the shadow processor register function as operands for a truth table stored in the memory and are used to select a function bit out from the memory. The selected function bit out represents a Boolean evaluation of the operands.

8612201, Dec 17, 2013

Apr 11, 2006

11/401641

Mikhail Bershteyn - Cupertino CA, US
Mitchell G. Poplack - San Jose CA, US
Beshara G. Elmufdi - Sunnyvale CA, US

Cadence Design Systems, Inc. - San Jose CA

G06F 9/455

703 28

A hardware emulation system having a heterogeneous cluster of processors is described. The apparatus for emulating a hardware design comprises a plurality of processors, where each processor performs a different function during an emulation cycle. The method performed by the apparatus comprises using a data fetch processor to retrieve data from a data array, evaluating the retrieved data using the data fetch processor to produce an output bit, supplying the output bit to an intracluster crossbar and using a data store processor to store the output bit in the data array.

20050027647, Feb 3, 2005

Jul 29, 2003

10/629098

Mikhail Bershteyn - Cupertino CA, US

G06F017/60

705038000

A method for prepayment of mortgage having an associated fixed interest rate where the payoff amount is lowered in proportion with the difference between said fixed interest rate and the market interest rate for similar new mortgages. A method for prepayment of mortgage having an associated fixed interest rate or an adjustable interest rate and an associated rate adjustment schedule where the payoff amount is lowered in proportion with the difference between the principal amount of debt and the price that such mortgage would fetch if sold in the secondary market. Methods are used to offer borrowers mortgage prepayment incentive in an economic environment characterized by increasing interest rates.