Mihai G Statovici

6367041, Apr 2, 2002

Sep 26, 2000

09/670992

Mihai G. Statovici - San Jose CA
Ronald J. Mack - Gilroy CA

Xilinx, Inc. - San Jose CA

G01R 3128

714724, 324 731

A method and software apparatus for implementing a dynamically modifiable test flow for integrated circuit devices that adapts to the characteristics of each processed device lot. A modified set of tests sufficient to ensure proper device function for a particular lot is performed, reducing test costs and increasing test capacity. The method and system of the invention periodically samples a predetermined sample number of devices using a full set of tests including a set of skippable tests. Depending upon the performance characteristics of the sample device group on the skippable tests, a number of skippable tests are skipped during a modified test flow. After a next set of devices is tested using the modified test flow, the full set of tests is again performed on another sample group, and the size and makeup of the modified test flow is adjusted according to the new results.

6552526, Apr 22, 2003

May 23, 2000

09/578793

Mihai G. Statovici - San Jose CA
Ronald J. Mack - Gilroy CA

Xilinx, Inc. - San Jose CA

G01R 1900

3241581, 324 7611

A method and system are provided for increasing the accuracy of AC parametric testing. The invention provides a method of precisely estimating signal propagation delay time in an integrated circuit testing apparatus, wherein a plurality of signal propagation delay time measurements are taken and additional delay times are estimated by linearly interpolating the measured delays. A desired test point (desired output voltage at a given time) is established. Using a sample device, a slope is established on a time vs. voltage plot for a line through the desired test point. Where a desired test point falls between strobe times on a tester, linear extrapolation is used to calculate what voltages must be tested for at the two bracketing strobe times in order to guarantee the desired performance at the desired test point. One or more devices are then tested for the calculated voltages at the corresponding bracketing strobe times.

7496820, Feb 24, 2009

Mar 7, 2006

11/369670

Conrad A. Theron - San Jose CA, US
Michael L. Simmons - Monte Sereno CA, US
Walter H. Edmondson - Morgan Hill CA, US
Mihai G. Statovici - Santa Barbara CA, US

Xilinx, Inc. - San Jose CA

G06F 11/00

714738, 714742, 714725, 714726, 714727, 714 25, 714724, 714741, 716 4, 716 5, 716 16, 716 17, 716 18, 703 15, 703 20

Method, apparatus, and computer readable medium for generating test vectors for an integrated circuit (IC) under test is described. In one example, a test function is specified using at least one elementary function that encapsulates program code associated with an architecture of the IC under test. An engine is configured with device description data for the IC under test. The engine is executed with the test function as parametric input to generate the test vectors. In one example, the IC under test comprises a programmable logic device (PLD) and the test vectors include configuration data for configuring a pattern in the PLD and at least one test vector for exercising the pattern. The test vectors may be applied directly to the device or through automatic test equipment (ATE). Alternatively, the test vectors may be applied to a IC design simulation of the device.

56616856, Aug 26, 1997

Sep 25, 1995

8/533131

Napoleon W. Lee - Milpitas CA
Derek R. Curd - San Jose CA
Sholeh Diba - Los Gatos CA
Prasad Sastry - Milpitas CA
Mihai G. Statovici - San Jose CA
Kameswara K. Rao - San Jose CA

Xilinx, Inc. - San Jose CA

G11C 700

36518522

An integrated programmable logic device (PLD) includes flash EPROM storage transistors. The PLD includes a multiplexor that selectively provides program, erase, or verify voltages to the storage transistors. The program, erase, and verify voltages may be supplied using external power supplies or may be generated internally by on-chip charge-pump generators. A configurable memory on the PLD is used to adjust the output voltages from each of the on-chip charge-pump generators.

56895160, Nov 18, 1997

Jun 26, 1996

8/670916

Ronald J. Mack - Gilroy CA
Derek R. Curd - San Jose CA
Sholeh Diba - Los Gatos CA
Napoleon W. Lee - Milpitas CA
Kameswara K. Rao - San Jose CA
Mihai G. Statovici - San Jose CA

Xilinx, Inc. - San Jose CA

G06F 1100

371 222

A programmable logic device (PLD) includes test circuitry compatible with the JTAG standard (IEEE Standard 1149. 1). The PLD also includes a programmable JTAG-disable bit that can be selectively programmed to disable the JTAG circuitry, leaving the PLD to operate as a conventional, non-JTAG-compatible PLD. The PLD also includes means for testing the JTAG test circuitry to determine whether the JTAG circuitry is defective, and means for programming the JTAG-disable bit to disable the JTAG circuitry if the testing means determines that the JTAG circuitry is defective.

59236027, Jul 13, 1999

Mar 19, 1998

9/044584

Mihai G. Statovici - San Jose CA
Ronald J. Mack - Gilroy CA

Xilinx, Inc. - San Jose CA

G11C 700

365201

A method is described for testing the programming function of integrated circuit device cells including floating gate elements. To accelerate the testing process, at most two programming pulses are needed, the two pulses being applied with the device at minimum and maximum power supply voltage levels specified for the device. First, the cell state after an initial programming pulse with the device at a minimum power supply voltage level, tested against a minimum reference voltage level, indicates whether the cell is programming properly. If not, testing ceases immediately and the device is rejected after the first pulse. Devices passing the first reading after the first pulse are subjected to a second reading at the target (higher) reference voltage. Devices passing after the second reading are designated as passing and are subjected to the next test in the test flow. Devices failing the second reading are subjected to a second programming pulse, applied with the device at the maximum power supply voltage level, the resulting cell state providing an indication of cell programming functionality.

63276348, Dec 4, 2001

Aug 25, 1998

9/139529

Mihai G. Statovici - San Jose CA

Xilinx, Inc. - San Jose CA

G06F 1338

710 74

A novel system and method are provided for storing a configuration data file for a programmable logic device such as an FPGA and for loading such a file into the device. The system and method of the present invention improves the performance of a bitstream storage apparatus by compressing the bitstream by a factor of about 5:1 to 10:1 before loading the bitstream into a storage unit, and then decompressing the bitstream, preferably within the storage unit, before forwarding the bitstream to the programmable device. In one embodiment, the decompression circuit is programmable, being able to utilize any of two or more different algorithms. In this embodiment, several different compression algorithms are evaluated, and the most efficient algorithm for that particular bitstream is utilized.

58257870, Oct 20, 1998

Nov 25, 1997

8/978163

Mihai G. Statovici - San Jose CA

Xilinx, Inc. - San Jose CA

G06F 1100

371 271

An improved circuit tester allows for increased storage of test vectors in existing memory structures by noting where segments of test vectors repeat and storing such segments only once, then further utilizing memory space corresponding to otherwise unused test channels. Switching circuitry is included to selectively forward signals to and from a designated, multi-source conductor.