20120131404, May 24, 2012
Ruben Ramirez - Hillsboro OR,
Michael J. Wiznerowicz - Hillsboro OR,
Sean T. Baartmans - Hillsboro OR,
Jason G. Sandri - Gilbert AZ,
In one embodiment, the present invention is directed to a logic analyzer such as may be implemented on a system-on-chip or another semiconductor device. The analyzer can include multiple lanes each having a filter to receive and filter debug data, a compressor to compress the debug data passed by the filter, a buffer, and a controller to store the compressed debug data into the buffer, where the compressed debug data can be stored without timing information. Other embodiments are described and claimed.