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Michael Wiznerowicz Phones & Addresses

  • 1836 NW Emerson Way, McMinnville, OR 97128 (503) 806-1210
  • 13456 Hawks Beard St, Portland, OR 97223 (503) 524-1725
  • 12989 SW Black Walnut St, Portland, OR 97224 (503) 598-0958
  • Tigard, OR
  • 13970 Scholls Ferry Rd, Beaverton, OR 97007 (503) 524-1725
  • 13970 SW Scholls Ferry Rd #101, Beaverton, OR 97007 (503) 524-1725
  • Federal Way, WA
  • Saginaw, MI
  • Minneapolis, MN
  • Chandler, AZ

Industries

Semiconductors

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Resumes

Michael Wiznerowicz Photo 1

Michael Wiznerowicz

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Location:
Portland, Oregon Area
Industry:
Semiconductors

Publications

Us Patents

On-Die Temperature Monitoring In Semiconductor Devices To Limit Activity Overload

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US Patent:
20060242447, Oct 26, 2006
Filed:
Mar 23, 2005
Appl. No.:
11/088445
Inventors:
Sivakumar Radhakrishnan - Portland OR, US
Michael Wiznerowicz - Beaverton OR, US
Jed Griffin - Forest Grove OR, US
Kapilan Maheswaran - Beaverton OR, US
Scott Rushford - Hillsboro OR, US
David Hotz - Beaverton OR, US
International Classification:
G06F 1/00
US Classification:
713501000
Abstract:
Thermal control for a controller in a data processing environment is described. In one embodiment, the invention includes detecting a temperature of a semiconductor device at a thermal sensor on the semiconductor device, comparing the detected temperature to a threshold, and generating a high interrupt if the temperature is above the threshold and a low interrupt if the temperature is below the threshold.

Providing An On-Die Logic Analyzer (Odla) Having Reduced Communications

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US Patent:
20120131404, May 24, 2012
Filed:
Nov 23, 2010
Appl. No.:
12/952822
Inventors:
Ruben Ramirez - Hillsboro OR, US
Michael J. Wiznerowicz - Hillsboro OR, US
Sean T. Baartmans - Hillsboro OR, US
Jason G. Sandri - Gilbert AZ, US
International Classification:
G01R 31/3177
G06F 11/25
US Classification:
714733, 714E11155
Abstract:
In one embodiment, the present invention is directed to a logic analyzer such as may be implemented on a system-on-chip or another semiconductor device. The analyzer can include multiple lanes each having a filter to receive and filter debug data, a compressor to compress the debug data passed by the filter, a buffer, and a controller to store the compressed debug data into the buffer, where the compressed debug data can be stored without timing information. Other embodiments are described and claimed.

System-On-Chip Secure Debug

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US Patent:
20150331043, Nov 19, 2015
Filed:
May 15, 2014
Appl. No.:
14/279007
Inventors:
Manoj R. Sastry - Portland OR, US
Enrico D. Carrieri - Rancho Cordova CA, US
Michael Neve de Mevergnies - Beaverton OR, US
Ioannis T. Schoinas - Portland OR, US
Michael J. Wiznerowicz - Tigard OR, US
International Classification:
G01R 31/3177
G06F 21/76
Abstract:
A system on chip (SOC) includes a policy generator to identify lifecycle data that identifies a lifecycle of the SOC and identify authentication data that identifies a particular user that is to debug the SoC. A particular policy is determined based on the lifecycle and identification of the particular user, and policy data is sent to at least one block of the SoC, the policy data identifying the particular policy. Debug access at the block is based on the particular policy.
Michael J Wiznerowicz from McMinnville, OR, age ~60 Get Report