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Meei-Ling Chiang

from Cupertino, CA
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Related to:
Elaine S Chou, 29Ching-Ping Chou, 57Chingping Chou, 57Caroline Chou, 27Meeiling Chiang, 57
Connected to:
Adam Chiang, 26Alison Chiang, 34Amber M Chiang, 49Anthony Y Chiang, 82Anton L Chiang, 54Belinda Chiang, 86Bryan A Chiang, 42Candy K Chiang, 38Carina K Chiang, 29Chenhuei J Chiang, 75

Meei-Ling Chiang Phones & Addresses

  • Cupertino, CA

Work

Company: Amd Position: Smts

Skills

Soc • Asic • Vlsi • Ic • Mixed Signal • Physical Design • Semiconductors • Verilog • Cmos • Eda • Circuit Design • Static Timing Analysis • Rtl Design • Low Power Design • Lvs • Processors • Serdes • Timing Closure • Drc • Pll • Primetime • Systemverilog • Functional Verification

Industries

Semiconductors

Resumes

Resumes

Meei-Ling Chiang Photo 1

Smts

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Location:
1099 Milky Way, Cupertino, CA 95014
Industry:
Semiconductors
Work:
AMD
SMTS
Skills:
Soc
Asic
Vlsi
Ic
Mixed Signal
Physical Design
Semiconductors
Verilog
Cmos
Eda
Circuit Design
Static Timing Analysis
Rtl Design
Low Power Design
Lvs
Processors
Serdes
Timing Closure
Drc
Pll
Primetime
Systemverilog
Functional Verification

Publications

Us Patents

Pipeline Analog To Digital (A/D) Converter With Relaxed Accuracy Requirement For Sample And Hold Stage

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US Patent:
6337651, Jan 8, 2002
Filed:
Feb 17, 2000
Appl. No.:
09/506284
Inventors:
Meei-Ling Chiang - San Jose CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H03M 138
US Classification:
341161, 340118, 340162
Abstract:
A pipeline analog to digital (A/D) converter. The pipeline A/D converter having a sample and hold amplifier stage, the sample and hold amplifier stage sampling an analog input signal during a first clock pulse signal. The pipeline A/D converter having an analog signal converter stage, the analog signal converter stage sampling the analog input signal during a first clock pulse signal. According to another aspect of the invention, the pipeline A/D converter converts an analog input signal into a digital representation of the analog input signal. The pipeline A/D converter has a clock generator, the clock generator generating a first clock pulse signal, a second clock pulse signal and a third clock pulse signal. A sample and hold stage samples an analog input signal during the pulse of the first clock signal and holds a sampled voltage signal during the pulse of the second clock signal. A first analog signal converter stage converts and latches the sampled and held voltage signal into a digital output during the pulse of the second clock signal, a most significant bit of the digital representation of the analog input signal being derived from the digital output.

Digital Logic Correction Circuit For A Pipeline Analog To Digital (A/D) Converter

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US Patent:
6359579, Mar 19, 2002
Filed:
Feb 17, 2000
Appl. No.:
09/506037
Inventors:
Meei-Ling Chiang - San Jose CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H03M 112
US Classification:
341155, 341118, 341156, 341161
Abstract:
A digital logic correction (DLC) circuit for a pipeline analog to digital (A/D) converter. The A/D converter having a plurality of stages, each stage producing at least a pair of digital output bits from which a digital representation of an analog input signal can be obtained. The DLC circuit has an adder, the adder having a plurality of inputs and an output. The DLC circuit has a plurality of digital delay sets, each digital delay set comprising at least one digital delay, an input of the digital delay set receiving a corresponding digital output bit and an output of the delay set providing a delayed digital output bit to a respective adder input. The DLC circuit has a clock generator, the clock generator providing clock signals to the DLC circuit to synchronize the arrival of the output of each digital delay set at the adder inputs during a data-valid-period. A primary clock signal is applied to the digital delay sets for every other stage. A secondary clock signal is applied to the remaining digital delay sets.

Variable Accuracy Pipeline Adc For Wlan Communications Devices

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US Patent:
7009548, Mar 7, 2006
Filed:
Dec 14, 2004
Appl. No.:
11/011510
Inventors:
Meei-Ling Chiang - Saratoga CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H03M 1/38
US Classification:
341161, 341155, 341131
Abstract:
A pipeline ADC (Analog to Digital Converter) unit is provided that has a first and a second multi-stage portion. The first multi-stage portion has a first plurality of converter stages for converting a first analog signal to a first digital signal having a first digital resolution. The second portion has a second plurality of converter stages to convert a second analog signal to a second digital signal having a second digital resolution. The second plurality includes the first plurality. The pipeline ADC unit selectively uses either the first plurality of stages alone, or the second plurality. The pipeline ADC unit may be used in a WLAN (Wireless Local Area Network) communication device.

Parallel Multiplexing Duty Cycle Adjustment Circuit With Programmable Range Control

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US Patent:
7545190, Jun 9, 2009
Filed:
May 1, 2007
Appl. No.:
11/742845
Inventors:
Meei-Ling Chiang - Saratoga CA, US
Sanjeev Maheshwari - San Jose CA, US
Emerson S. Fang - Fremont CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H03K 3/017
US Classification:
327175, 327172
Abstract:
A receive interface circuit includes a duty cycle adjustment circuit that adjusts the duty cycle of a reference clock signal based, at least in part, on a selected number of duty cycle adjustment units and a selected range of duty cycle adjustment. The duty cycle adjustment circuit may select as the reference clock signal one of a clock signal and at least a lower version of the clock signal in parallel with the duty cycle adjustment.

Phase Select Circuit With Reduced Hysteresis Effect

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US Patent:
7750711, Jul 6, 2010
Filed:
May 1, 2007
Appl. No.:
11/742860
Inventors:
Sanjeev Maheshwari - San Jose CA, US
Meei-Ling Chiang - Saratoga CA, US
Emerson S. Fang - Fremont CA, US
Assignee:
Globalfoundries Inc. - Grand Cayman
International Classification:
H03H 11/26
US Classification:
327276, 327278
Abstract:
A phase signal select circuit includes a supporting path coupled to a tri-state inverter circuit. The supporting path reduces effects of hysteresis on signal transfer. An apparatus includes at least one input node responsive to a respective one of at least one input signal. The apparatus includes at least one circuit coupled to a respective one of the at least one input node and coupled to an output node. Individual ones of the at least one circuit are configured to provide a version of the respective input signal to the output node in response to a first state of a respective select signal. The apparatus includes at least one second circuit coupled to a respective one of the at least one circuit. The at least one second circuit is configured to toggle nodes of the at least one circuit in response to a second state of the respective select signal.

Test Techniques For A Delay-Locked Loop Receiver Interface

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US Patent:
7817761, Oct 19, 2010
Filed:
Jun 1, 2007
Appl. No.:
11/756674
Inventors:
Meei-Ling Chiang - Saratoga CA, US
Dwight K. Elvey - Sunnyvale CA, US
Sanjeev Maheshwari - San Jose CA, US
Emerson S. Fang - Fremont CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H04L 7/00
H03L 7/06
US Classification:
375356, 327158
Abstract:
An integrated circuit includes a variable delay circuit configured to generate at least one delayed clock signal based on a first clock signal and a first control signal. The integrated circuit includes a control circuit configured to generate a count value based on a second input signal and a second control signal. The first clock signal is a first version of the at least one delayed clock signal. At least one of the second input signal and the second control signal is a second version of the at least one delayed clock signal and the count value is indicative of a frequency characteristic of the at least one delayed clock signal. The integrated circuit is configured to monotonically vary the first control signal over a range of values and the count value is determined for individual values of the control signal.

Automatic Amplitude Control For Voltage Controlled Oscillator

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US Patent:
8134417, Mar 13, 2012
Filed:
Jun 10, 2010
Appl. No.:
12/813071
Inventors:
Meei-Ling Chiang - Cupertino CA, US
Dennis M. Fischette - Mountain View CA, US
Alvin Leng Sun Loke - Ft. Collins CO, US
Michael M. Oshima - Los Altos CA, US
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H03B 5/12
H03L 5/00
US Classification:
331109, 331117 FE, 331177 V, 331179, 331183
Abstract:
A circuit and method for calibrating a VCO (voltage controlled oscillator) is disclosed. In one embodiment, a circuit includes a VCO and a bias control circuit coupled to a tail node of the VCO. An amplitude control unit may also be coupled to the tail node, wherein the amplitude control unit is configured to determine the amplitude of a VCO output signal based on a voltage present on the tail node. The amplitude control unit may also be configured to generate a bias voltage based on the amplitude of the VCO output signal and a target voltage. The bias control circuit may be coupled to receive the bias voltage from the amplitude control unit and may be further configured to adjust the voltage on the tail node based on the received bias voltage.

Pipeline Analog To Digital (A/D) Converter With Relaxed Accuracy Requirement For Sample And Hold Stage

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US Patent:
62950169, Sep 25, 2001
Filed:
Feb 17, 2000
Appl. No.:
9/506208
Inventors:
Meei-Ling Chiang - San Jose CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H03M 138
US Classification:
341161
Abstract:
A pipeline analog to digital (A/D) converter for converting an analog input signal into a digital representation of the analog signal. The pipeline A/D converter has a sample and hold stage, the sample and hold stage sampling and holding the analog input signal and outputting a sampled and held signal. The pipeline A/D converter also has a first analog signal converter stage, the first analog converter stage producing a digital output based on the sampled and held signal, from which a most significant bit of the digital representation of the analog input signal is derived. The first analog converter stage produces a residue signal based on a comparison of the analog input signal and an analog representation of the digital output. The pipeline A/D converter has at least one additional stage, the additional stage producing a subsequent digital output based on the residue signal produced by the first analog signal converter stage, at least one bit which is less significant than the most significant bit being derived from the subsequent digital output.
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Meei-Ling Chiang from Cupertino, CA Get Report