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Massimo V Fischetti

from Putnam Valley, NY
Age ~72
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Also known as:
Massi Fischetti, Fischetti Massi
Phone and address:
24 Stephen Smith Dr, Tompkins Corners, NY 10579
Related to:
M Fischetti, 72Alessandra F Fischetti, 72M Fischetti, 36Alice G Fischetti, 32Sebastian N Fischetti, 36
Connected to:
Dawn M Fischetto, 62Gene D Fischetti, 76Jack Fischetti, 59Jeremy M Fischetti, 45Megan K Fischetti, 41Stephanie M Fischette, 63Theresa L Fischette, 69Damon J Fischio, 35John V Fischione, 67Deborah L Fischkelta, 60

Massimo Fischetti Phones & Addresses

  • 24 Stephen Smith Dr, Putnam Valley, NY 10579
  • 280 W Renner Rd APT 4223, Richardson, TX 75080 (914) 528-2634
  • 280 Renner Rd, Richardson, TX 75080
  • Mohegan Lake, NY
  • Yorktown, NY
  • Shenorock, NY

Resumes

Resumes

Massimo Fischetti Photo 1

Professor

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Location:
Dallas, TX
Industry:
Higher Education
Work:
University of Texas at Dallas
Professor
University of Massachusetts Amherst Jan 2005 - Aug 2010
Professor
Ibm Jan 1983 - Jan 2005
Research Staff Member
Education:
Uc Santa Barbara 1975 - 1978
Doctorates, Doctor of Philosophy, Physics, Philosophy
Skills:
Simulations
Physics
Semiconductors
Nanotechnology
Characterization
Materials Science
Mathematical Modeling
Electronics
Science
Latex
Thin Films
Research
Nanomaterials
Cmos
Numerical Analysis
Scientific Computing
Fortran
Monte Carlo Simulation
R&D
Vlsi
Solid State Physics
Mathematica
Nanofabrication
Modeling
Microfabrication
Research and Development
Languages:
Italian
French
Massimo Fischetti Photo 2

Professor

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Location:
Dallas, TX
Industry:
Higher Education
Work:
University of Texas at Dallas
Professor

Publications

Us Patents

Enhancement Of Electron And Hole Mobilities In <110> Si Under Biaxial Compressive Strain

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US Patent:
7161169, Jan 9, 2007
Filed:
Nov 3, 2004
Appl. No.:
10/980220
Inventors:
Victor Chan - New Paltz NY, US
Massimo V. Fischetti - Putnam Valley NY, US
John M. Hergenrother - Ridgefield CT, US
Meikei Leong - Wappingers Falls NY, US
Rajesh Rengarajan - Fishkill NY, US
Alexander Reznicek - Mount Kisco NY, US
Paul M. Solomon - Yorktown Heights NY, US
Chun-yung Sung - Poughkeepsie NY, US
Min Yang - Yorktown Heights NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 29/06
H01L 31/0328
US Classification:
257 18, 257 19, 257E29193
Abstract:
The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.

Enhancement Of Electron And Hole Mobilities In <110> Si Under Biaxial Compressive Strain

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US Patent:
7314790, Jan 1, 2008
Filed:
Dec 18, 2006
Appl. No.:
11/612309
Inventors:
Victor Chan - New Paltz NY, US
Massimo V. Fischetti - Putnam Valley NY, US
John M. Hergenrother - Ridgefield CT, US
Meikei Ieong - Wappingers Falls NY, US
Rajesh Rengarajan - Fishkill NY, US
Alexander Reznicek - Mount Kisco NY, US
Paul M. Solomon - Yorktown Heights NY, US
Chun-yung Sung - Poughkeepsie NY, US
Min Yang - Yorktown Heights NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/336
US Classification:
438198, 438680, 257 18, 257E21102
Abstract:
The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.

Enhancement Of Electron And Hole Mobilities In <110> Si Under Biaxial Compressive Strain

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US Patent:
7462525, Dec 9, 2008
Filed:
Oct 25, 2007
Appl. No.:
11/924024
Inventors:
Victor Chan - New Paltz NY, US
Massimo V. Fischetti - Putnam Valley NY, US
John M. Hergenrother - Ridgefield CT, US
Meikei Ieong - Wappingers Falls NY, US
Rajesh Rengarajan - Fishkill NY, US
Alexander Reznicek - Mount Kisco NY, US
Paul M. Solomon - Yorktown Heights NY, US
Chun-yung Sung - Poughkeepsie NY, US
Min Yang - Yorktown Heights NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/8234
US Classification:
438198, 438680, 257 18, 257 19, 257E21102, 257E29193
Abstract:
The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.

Enhancement Of Electron And Hole Mobilities In <110> Si Under Biaxial Compressive Strain

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US Patent:
7943486, May 17, 2011
Filed:
May 6, 2008
Appl. No.:
12/115731
Inventors:
Victor Chan - New Paltz NY, US
Massimo V. Fischetti - Putnam Valley NY, US
John M. Hergenrother - Ridgefield CT, US
Meikei Ieong - Wappingers Falls NY, US
Rajesh Rengarajan - Fishkill NY, US
Alexander Reznicek - Mount Kisco NY, US
Paul M. Solomon - Yorktown Heights NY, US
Chun-yung Sung - Poughkeepsie NY, US
Min Yang - Yorktown Heights NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/30
US Classification:
438458
Abstract:
The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.

Higher Performance Cmos On (110) Wafers

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US Patent:
7968946, Jun 28, 2011
Filed:
May 16, 2008
Appl. No.:
12/122227
Inventors:
Massimo V. Fischetti - Putnam Valley NY, US
Qiqing C. Ouyang - Yorktown Heights NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/70
US Classification:
257369, 438198, 257E23141, 257E2124
Abstract:
A semiconductor (e. g. , complementary metal oxide semiconductor (CMOS)) structure formed on a (110) substrate that has improved performance, in terms of mobility enhancement is provided. In accordance with the present invention, the inventive structure includes at least one of a single tensile stressed liner, a compressively stressed shallow trench isolation (STI) region, or a tensile stressed embedded well, which is used in conjunction with the (110) substrate to improve carrier mobility of both nFETs and pFETs. The present invention also relates to a method of providing such structures.

Germanium Field Effect Transistor And Method Of Fabricating The Same

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US Patent:
20030190791, Oct 9, 2003
Filed:
Apr 4, 2002
Appl. No.:
10/116568
Inventors:
Massimo Fischetti - Putnam Valley NY, US
Steven Laux - Yorktown Heights NY, US
Paul Solomon - Yorktown Heights NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L021/336
US Classification:
438/305000
Abstract:
A method (and structure) for an electronic chip having at least one layer of material for which a carrier mobility of a first carrier type is higher in a first crystal surface than in a second crystal surface and for which a carrier mobility of a second carrier type is higher in the second crystal surface than the first crystal surface includes a first device having at least one component fabricated on the first crystal surface of the material, wherein an activity of the component of the first device involves primarily the first carrier type, and a second device having at least one component fabricated on the second crystal surface of the material, wherein an activity of the component of the second device involves primarily the second carrier type.

Higher Performance Cmos On (110) Wafers

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US Patent:
20070158739, Jul 12, 2007
Filed:
Jan 6, 2006
Appl. No.:
11/327256
Inventors:
Massimo Fischetti - Putnam Valley NY, US
Qiqing Ouyang - Yorktown Heights NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/8238
US Classification:
257327000, 438199000
Abstract:
A semiconductor (e.g., complementary metal oxide semiconductor (CMOS)) structure formed on a (110) substrate that has improved performance, in terms of mobility enhancement is provided. In accordance with the present invention, the inventive structure includes at least one of a single tensile stressed liner, a compressively stressed shallow trench isolation (STI) region, or a tensile stressed embedded well, which is used in conjunction with the (110) substrate to improve carrier mobility of both nFETs and pFETs. The present invention also relates to a method of providing such structures.

Enhancement Of Electron And Hole Mobilities In <110> Si Under Biaxial Compressive Strain

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US Patent:
20080044987, Feb 21, 2008
Filed:
Oct 25, 2007
Appl. No.:
11/924015
Inventors:
Victor Chan - New Paltz NY, US
Massimo Fischetti - Putnam Valley NY, US
John Hergenrother - Ridgefield CT, US
Meikei Ieong - Wappingers Falls NY, US
Rajesh Rengarajan - Fishkill NY, US
Alexander Reznicek - Mount Kisco NY, US
Paul Solomon - Yorktown Heights NY, US
Chun-yung Sung - Poughkeepsie NY, US
Min Yang - Yorktown Heights NY, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
H01L 21/20
US Classification:
438492000, 257E21090
Abstract:
The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.
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Massimo V Fischetti from Putnam Valley, NY, age ~72 Get Report