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Masaaki Kaneko

from Austin, TX
Age ~57
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Also known as:
Kaneko Masaaki
Related to:
Naomi Kaneko
Connected to:
Akira J Kaneko, 48Brian Y Kaneko, 52Cassie M Kaneko, 37Hiroshi Kaneko, 63Keola H Kanekoa, 41Koji Kaneko, 51Kristin L Kaneko, 53Leona T Kaneko, 96Miyuki Kaneko, 60Sarah L Kaneko, 42

Masaaki Kaneko Phones & Addresses

  • Austin, TX
  • 7720 Oconnor Dr, Round Rock, TX 78681 (512) 218-1974

Resumes

Resumes

Masaaki Kaneko Photo 1

Design Engineering Manager

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Location:
Austin, TX
Industry:
Semiconductors
Work:
TOSHIBA
DESIGN ENGINEERING MANAGER
Masaaki Kaneko Photo 2

Masaaki Kaneko

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Publications

Wikipedia

Masaaki Kaneko

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Masaaki Kaneko (born 8 July 1940) is a Japanese wrestler and Olympic champion in Freestyle wrestling. [edit] Olympics. Kaneko competed at the 1968 Summer ...

Wrestling at the 1968 Summer Olympics Men's freestyle 63 kg ...

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Gold, Masaaki Kaneko Japan (JPN). Silver, Enyu Todorov Bulgaria (BUL). Bronze, Shamseddin Seyed-Abbasi Iran (IRI). [edit] Tournament results ...

Us Patents

Systems And Methods For Controlling A Fuse Programming Current In An Ic

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US Patent:
7405590, Jul 29, 2008
Filed:
Jul 18, 2007
Appl. No.:
11/779411
Inventors:
Masaaki Kaneko - Round Rock TX, US
Assignee:
Kabushiki Kaisha Toshiba - Tokyo
International Classification:
G06F 7/38
H03K 19/173
US Classification:
326 38, 326 37, 326 30
Abstract:
Systems and methods for controlling the programming current directed through a fuse or set of fuses in a device such as an integrated circuit. One embodiment comprises a method for applying different currents to a set of calibration fuses, identifying which currents cut the corresponding fuses without destroying them, and selecting one of the identified currents to use in programming one or more target fuses. In one embodiment, fuses that are cut but not destroyed are identified by passing the same read current through each of the calibration fuses and comparing resulting voltages to reference voltages which correspond to impedances between the impedances of the possible fuse states (uncut, cut and destroyed. ) Fuse voltages between the reference voltages identify fuses which are cut but not destroyed.

Systems And Methods For Level Shifting Using Ac Coupling

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US Patent:
7511554, Mar 31, 2009
Filed:
Jun 18, 2007
Appl. No.:
11/764262
Inventors:
Masaaki Kaneko - Round Rock TX, US
David W. Boerstler - Round Rock TX, US
Eskinder Hailu - Sunnyvale CA, US
Jieming Qi - Austin TX, US
Assignee:
Kabushiki Kaisha Toshiba - Tokyo
International Business Machines Corporation - Armonk NY
International Classification:
H03L 5/00
US Classification:
327333, 326 63, 326 80
Abstract:
Systems and methods for conveying signals between integrated circuit (IC) components in domains having different supply voltages. AC coupling is used to increase the speed at which the common mode voltage of a signal is shifted from one level to another. One embodiment comprises a method for level shifting a binary signal in an IC. This method includes receiving an input binary signal and decoupling its AC component from its common mode component. A second common mode component is added to the AC component, providing a binary output signal. The common mode voltage of the input signal may be greater (or smaller) than that of the output signal. In one embodiment of the method, duty cycle compensation (DCC) is performed. The DCC drives the duty cycle toward a desired value.

Systems And Methods For Pll Linearity Measurement, Pll Output Duty Cycle Measurement And Duty Cycle Correction

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US Patent:
7642863, Jan 5, 2010
Filed:
Dec 7, 2007
Appl. No.:
11/952706
Inventors:
Masaaki Kaneko - Round Rock TX, US
David W. Boerstler - Round Rock TX, US
Eskinder Hailu - Sunnyvale CA, US
Jieming Qi - Austin TX, US
Assignee:
Kabushiki Kaisha Toshiba - Tokyo
International Business Machines Corporation - Armonk NY
International Classification:
G01R 23/00
H03L 7/06
US Classification:
331 44, 331 1 A, 331 14, 331 17, 331 18, 331 25
Abstract:
Systems and methods for enabling the determination of voltage controlled oscillator (VCO) linearity, duty cycle determination and duty cycle correction in phase locked loop circuits (PLL's. ) One embodiment comprises a method including the steps of determining the frequency response of a PLL's VCO as a function of duty cycle, applying a signal based on the VCO output to the VCO input, measuring the resulting frequency of the VCO output signal, determining the duty cycle corresponding to the measured frequency, and configuring a duty cycle correction unit correct the duty cycle of the VCO output signal to about 50%. Determining the frequency response of the VCO may include, for each of several different duty cycle values between 0% and 100%, applying the VCO input signal to the VCO and determining the corresponding frequency of the VCO output signal. This may also be done for duty cycles of 0% and 100%.

Wide Range Interpolative Voltage Controlled Oscillator

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US Patent:
7642868, Jan 5, 2010
Filed:
Jun 15, 2007
Appl. No.:
11/763997
Inventors:
Masaaki Kaneko - Round Rock TX, US
Assignee:
Kabushiki Kaisha Toshiba - Tokyo
International Classification:
H03B 27/00
US Classification:
331 57, 331177 R, 331185
Abstract:
Systems and methods for increasing the frequency range of an output signal generated by a VCO, where one or more variable delay units are incorporated into an interpolative VCO to decrease the minimum frequency at which the VCO oscillates. In one embodiment, the VCO includes a ring of serially connected inverters, a set of bypass circuits and a set of variable delay units. The bypass circuits are coupled to the ring of serially connected inverters to bypass one or more of the serially connected inverters when enabled. Each variable delay unit delays signal transitions at the input of a corresponding one of the serially connected inverters by a variable amount. The variable delay units may be positioned in series with the ring of inverters, in parallel with the bypass paths, or in parallel with corresponding inverters in the ring of inverters.

Systems And Methods For Determining The State Of A Programmable Fuse In An Ic

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US Patent:
7701226, Apr 20, 2010
Filed:
Jul 3, 2007
Appl. No.:
11/772882
Inventors:
Masaaki Kaneko - Round Rock TX, US
Assignee:
Kabushiki Kaisha Toshiba - Tokyo
International Classification:
G01R 31/02
US Classification:
324550, 324713, 327525, 3652257, 257529
Abstract:
Systems and methods for detecting the mode (a. k. a. , state) of a fuse or set of fuses in a device such as an integrated circuit. One embodiment comprises a method for determining three fuse states (uncut, cut, and destroyed) by comparing the fuse voltage with two reference voltages. Each fuse state has a different (indicative) impedance and is associated with a fuse voltage. The fuse voltage is below, between, or above two reference voltages, thereby determining the fuse state. One embodiment includes the fuse in series with a read transistor as well as two reference voltage generators, each comprising a resistor and a transistor (equivalent to the read transistor). Both resistors' impedances are greater than the uncut fuse impedance and one is less than the cut fuse impedance. Two comparators are used to bracket the fuse voltage, indicating that the fuse is uncut, cut, or destroyed.

Phase Locked Loop With Temperature And Process Compensation

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US Patent:
7737794, Jun 15, 2010
Filed:
May 14, 2008
Appl. No.:
12/120331
Inventors:
David W. Boerstler - Round Rock TX, US
Masaaki Kaneko - Round Rock TX, US
Toshiyuki Ogata - Tokyo, JP
Jieming Qi - Austin TX, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 23/02
US Classification:
331 44, 331 17, 331176
Abstract:
Mechanisms are provided for compensating for process and temperature variations in a circuit. The mechanisms may select at least one resistor in a plurality of resistors in the circuit to provide a resistance value for generating a calibration voltage input to the circuit to compensate for variations in process. A reference signal may be compared to a feedback signal generated by the circuit based on the calibration signal. A determination is made as to whether the feedback signal is within a tolerance of the reference signal and, if so, an identifier of the selected at least one resistor is stored in a memory device coupled to the circuit. The circuit may be operated using the selected at least one resistor based on the identifier stored in the memory device. An apparatus and integrated circuit device utilizing these mechanisms are also provided.

Duty Cycle Measurement For Various Signals Throughout An Integrated Circuit Device

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US Patent:
7895005, Feb 22, 2011
Filed:
Nov 20, 2007
Appl. No.:
11/942966
Inventors:
David W. Boerstler - Round Rock TX, US
Eskinder Hailu - Austin TX, US
Masaaki Kaneko - Round Rock TX, US
Jieming Qi - Austin TX, US
Bin Wan - Pittsburgh PA, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 13/00
US Classification:
702 66, 702 79, 702 89, 702107, 702125, 702176, 702178, 327174, 327175
Abstract:
A mechanism is provided for measuring the absolute duty cycle of a signal anywhere on an integrated circuit device. The mechanism employs a circuit having a plurality of substantially identical pulse shaper elements, each of which expand the pulse of an input signal whose duty cycle is to be measured by a same amount. The outputs of the pulse shaper elements may be coupled to substantially identical divider circuits whose outputs are coupled to a multiplexer that selects two inputs for output to a set of master/slave configured flip-flops, one input serving as a clock and the other as data to the flip-flops. The flip-flops sample the divider outputs selected by the multiplexer to detect if the dividers have failed or not. The outputs of the flip-flops are provided to an XOR gate which outputs a duty cycle signal indicative of the duty cycle of the input signal.

Absolute Duty Cycle Measurement

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US Patent:
7904264, Mar 8, 2011
Filed:
Nov 12, 2007
Appl. No.:
11/938456
Inventors:
David W. Boerstler - Round Rock TX, US
Eskinder Hailu - Austin TX, US
Masaaki Kaneko - Round Rock TX, US
Jieming Qi - Austin TX, US
Bin Wan - Pittsburgh PA, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G01R 35/00
G01R 15/00
US Classification:
702 79, 702 57, 702 85, 702 89, 327175, 327176
Abstract:
A mechanism for measuring the absolute duty cycle of a signal is provided. A non-inverted path from a signal source is selected and various DCC circuit setting indices are cycled through until a divider, coupled to the output of the DCC circuit, fails. A first minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of the failure. An inverted path from the signal source is selected and the various DCC circuit setting indices are cycled through again until the divider fails. A second minimum pulse width at which the divider fails is then determined based on the index value of the DCC circuit at the time of this second failure. The duty cycle is then calculated based on a difference of the first and second minimum pulse width values.
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Masaaki Kaneko from Austin, TX, age ~57 Get Report