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Mark Scheitrum Phones & Addresses

  • 2957 Faircliff Ct, San Jose, CA 95125 (408) 448-6296
  • 4958 Union St, San Jose, CA 95124 (408) 796-7422
  • Tamiment, PA
  • Bend, OR

Work

Company: Atessa, inc. Nov 2010 Position: Chief operations officer

Education

Degree: Master of Science, Masters, Bachelors, Bachelor of Science School / High School: Lehigh University Specialities: Electrical Engineering, Computer Science

Skills

Rtos • Embedded Systems • Security • R&D • Business Development

Languages

English

Industries

Computer Hardware

Resumes

Resumes

Mark Scheitrum Photo 1

Chief Operations Officer

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Location:
P/O Box 1113, Laguna Beach, CA
Industry:
Computer Hardware
Work:
Atessa, Inc.
Chief Operations Officer

Cpu Technology, Inc. Jan 2003 - Aug 2010
Vice President Engineering

Chameleon Systems Jan 2000 - Jan 2002
Vice President Systems Engineering

Cadence Design Systems Jan 1995 - Jan 1999
Group Director, Design Services

Cpu Technology, Inc. Jan 1992 - Jan 1995
Vice President Development
Education:
Lehigh University
Master of Science, Masters, Bachelors, Bachelor of Science, Electrical Engineering, Computer Science
Skills:
Rtos
Embedded Systems
Security
R&D
Business Development
Languages:
English

Business Records

Name / Title
Company / Classification
Phones & Addresses
Mark Scheitrum
PRECURSYS LLC
Engineering Services
2957 Faircliff St, San Jose, CA 95125
2957 Faircliff Ct, San Jose, CA 95125
Mark Scheitrum
President
INTERACTIVE WATER SYSTEMS, INC
2957 Faircliff Ct, San Jose, CA 95125

Publications

Us Patents

Multiprocessors System For Selectively Wire-Oring A Combination Of Signal Lines And Thereafter Using One Line To Control The Running Or Stalling Of A Selected Processor

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US Patent:
58322531, Nov 3, 1998
Filed:
Dec 6, 1993
Appl. No.:
8/163442
Inventors:
Edward C. King - Pleasanton CA
Alan G. Smith - Dublin CA
Mark E. Scheitrum - San Jose CA
Assignee:
CPU Technology, Inc. - Pleasanton CA
International Classification:
G06F 1300
US Classification:
395553
Abstract:
The present invention provides for a computer system having a plurality of parallel processor units. The processor units are connected in common to a signal line with each processor capable of setting a first signal level on the line and monitoring the line in response to instructions to the processor. This allows each processor unit to be notified of the completion of a parallel operation by other participating processor units upon a second signal level on the signal line. More than one signal lines may be connected between the parallel processor units to provide synchronization of different parallel operations between different processor units.
Mark E Scheitrum from San Jose, CA, age ~71 Get Report