Mark A Kovalan

6453374, Sep 17, 2002

Mar 30, 1999

09/281584

Mark A. Kovalan - Cedar Rapids IA
Bryon L. Wiscons - Marion IA
John L. Persick - Robins IA
Douglas R. Johnson - Cedar Rapids IA
Gregory E. Dunn - Marion IA
Stephen I. Kotalik - RR Midway IA

Rockwell Collins, Inc. - Cedar Rapids IA

G06F 1300

710100, 326 30

A bus system including a bus user apparatus and a method for communicating via the bus system are disclosed. The bus user apparatus includes means for means for selectively coupling a transmitter to the transmission line according to a protocol of the bus system. The bus system provides bi-directional communication over a single transmission line. The transmitter of the transmitting device is coupled to the transmission line during transmission. Upon completion of transmission, the transmitting device sends a permission to transmit signal to the next transmitting device according to the protocol, and decouples its transmitter from the transmission line. The next transmitting device couples its transmitter to the transmission line and begins transmission of data. Multiple bus users, both transmitters and receivers, are accommodated by the bus system, and bi-directional communication is supported. Further, the data transmission rate may be increased by selectively coupling the transmitter of a receiving device to the transmission line to provide a termination impedance on the transmission line.

6694382, Feb 17, 2004

Aug 21, 2000

09/643060

Mark A. Kovalan - Cedar Rapids IA
Bryon L. Wiscons - Marion IA
Ronald W. Aull - Cedar Rapids IA
John L. Persick - Robins IA

Rockwell Collins, Inc. - Cedar Rapids IA

G06F 300

710 5, 710 33, 710 65

A data transfer mechanism for directing data signals from signal-producing elements to signal-receiving elements is disclosed. The data transfer mechanism includes a plurality of input ports, with each input port being connected to a signal-producing element, and a plurality of output ports, with each output port being connected to a signal-receiving element. Each data signal that enters the data transfer mechanism through one of the plurality of input ports has data identification information associated therewith. The, data transfer mechanism directs the data signal to at least one of the plurality of output ports according to the data identification information associated with the data signal.

7852235, Dec 14, 2010

Apr 28, 2008

12/150402

Douglas R. Johnson - Cedar Rapids IA, US
James J. Corcoran - Cedar Rapids IA, US
Eric J. Danielson - Iowa City IA, US
John W. Roltgen - Cedar Rapids IA, US
Mark A. Kovalan - Cedar Rapids IA, US
Corydon J. Carlson - Cedar Rapids IA, US
John L. Persick - Robins IA, US
Cleveland C. Gilbert - Cedar Rapids IA, US
Samir S. Hemaidan - Cedar Rapids IA, US
Shawn M. Stanger - Marion IA, US

Rockwell Collins, Inc. - Cedar Rapids IA

G08B 21/00
G08B 29/00
G06F 11/00
G01C 23/00

340945, 340506, 340507, 340508, 340522, 701 3, 701 14, 714 11, 714 12

A method of comparing output information from dissimilar processors includes storing a task in a first memory and storing the task in a second memory at substantially the same time as the first memory. The time of the storing being is controlled by a first arbitration logic and a second arbitration logic. The method also includes receiving the task by a first processor from the first memory and receiving the task by a second processor from the memory at substantially the same time as the first processor. The time being received is controlled by a first arbitration logic and a second arbitration logic. The second processor being dissimilar to the first processor. The method further includes computing a first output by the first processor based on the task and computing a second output by the second processor based on the task. The method still further includes, synchronizing the first and second outputs so that the first and second outputs are output at substantially the same time. The synchronizing is controlled by the first and second arbitration logic.

8015390, Sep 6, 2011

Mar 19, 2008

12/077599

James J. Corcoran - Cedar Rapids IA, US
Eric J. Danielson - Iowa City IA, US
Samir S. Hemaidan - Cedar Rapids IA, US
John W. Roltgen - Cedar Rapids IA, US
James E. Sisson - Robins IA, US
Mark A. Kovalan - Cedar Rapids IA, US
Mark C. Singer - Cedar Rapids IA, US

Rockwell Collins, Inc. - Cedar Rapids IA

G06F 11/00

712 12

A flight control system includes an output device, a first processor, and a second processor. The second processor is dissimilar to the first processor. The flight control system also includes a first arbitration device coupled to the first processor and a second arbitration device coupled to the second processor. The second arbitration device is configured to coordinate transaction synchronization with the first arbitration device and the first arbitration device is configured to coordinate transaction synchronization with the second arbitration device. A comparator processor is coupled to the first arbitration device and the second arbitration device. The comparator processor is configured to compare transaction synchronized outputs of the first and second processors and the comparator processor effectuates a command to the output device if the comparison is valid.

8078055, Dec 13, 2011

May 5, 2008

12/151249

Daniel E. Mazuk - Marion IA, US
Peter J. Morgan - Glenelg MD, US
David A. Miller - Swisher IA, US
Nicholas H. Bloom - Cedar Rapids IA, US
Mark A. Kovalan - Cedar Rapids IA, US

Rockwell Collins, Inc. - Cedar Rapids IA

H04B 10/20

398 66, 398113

The present disclosure is directed to a passive optical avionics network system and method. A passive avionics network may comprise: (a) an optical line terminal (OLT); (b) at least one optical network unit (ONU); (c) a fiber optic bus operably coupling the OLT and the ONU; and (d) an avionics module operably coupled to the ONU. An integrated modular avionics (IMA) system may comprise: (a) a line-replaceable unit (LRU), the LRU comprising: (i) a processing unit; and (ii) an optical line terminal (OLT); (b) at least one optical network unit (ONU); (c) a fiber optic bus operably coupling the LRU and the ONU; and (d) an avionics module operably coupled to the ONU. A method for avionics network communication may comprise: (a) providing avionics data; (b) transmitting the avionics data via a fiber optic network; (c) receiving the avionics data; and (d) controlling functionality of an avionics module according to the avionics data.

8306421, Nov 6, 2012

Jul 21, 2008

12/220014

Daniel E. Mazuk - Marion IA, US
David A. Miller - Swisher IA, US
Mark A. Kovalan - Cedar Rapids IA, US

Rockwell Collins, Inc. - Cedar Rapids IA

H04B 10/20

398 66, 398168

The present disclosure is directed to a passive optical avionics network system and method. A avionics network system may comprise: (a) a passive optical network, the passive optical network comprising an optical repeater; and (b) an avionics module operably coupled to the passive optical network. An integrated modular avionics (IMA) system may comprise: (a) a line-replaceable unit (LRU), the LRU comprising: (i) a processing unit; and (ii) an optical line terminal (OLT); (b) an optical repeater; (c) at least one optical network unit (ONU); and an avionics module operably coupled to the at least one ONU. A method for avionics network communication may comprise: (a) receiving optical avionics data signals; (b) monitoring the optical avionics data signals for compliance with a communications protocol; and (c) regulating transmission of the optical avionics data signals according to compliance with the communications protocol.

46202773, Oct 28, 1986

Feb 28, 1983

6/470695

Jimmie L. Fisher - Phoenix AZ
Mark A. Kovalan - Cedar Rapids IA
Bryon L. Wiscons - Marion IA

Rockwell International Corporation - El Segundo CA

G06F 1200

364200

A circuit and technique of operation thereof are disclosed for a multimaster CPU system wherein a memory may be accessed during program operation in an average time less than that of the memory access time specification. This technique has particular usefulness in programs contained in relatively slow read-only-memory wherein a significant portion of the addresses related to memory are sequential. In optimum utilization, each master CPU has a dedicated PROM card which can only be enabled by the specified CPU. This configuration prevents additional master CPU's from interfering with the time saving benefits of early memory addressing.