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Maria J Garzaran

from Champaign, IL
Age ~56
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Connected to:
Benay B Garzarelli, 67Emily A Garzarelli, 46Richard A Garzarelli, 34Manfred Garzaro, 51Glenn G Garze, 52Mona H Garzelloni, 95Samantha Garzes, 34Dawn Garzia, 60Nicholas A Garziano, 43Tommaso Garziano, 85

Maria Garzaran Phones & Addresses

  • 3012 Weeping Cherry Dr, Champaign, IL 61822 (217) 356-8503
  • Urbana, IL

Work

Company: University of illinois at urbana-champaign Position: Research assistant professor

Education

School / High School: Universidad de Zaragoza 1995 to 2002

Languages

Spanish • English • French

Industries

Research

Resumes

Resumes

Maria Garzaran Photo 1

Principal Engineer

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Location:
Urbana, IL
Industry:
Research
Work:
University of Illinois at Urbana-Champaign
Research Assistant Professor
Education:
Universidad de Zaragoza 1995 - 2002
Languages:
Spanish
English
French

Publications

Us Patents

Minimizing Usage Of Hardware Counters In Triggered Operations For Collective Communication

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US Patent:
20190213146, Jul 11, 2019
Filed:
Mar 14, 2019
Appl. No.:
16/353759
Inventors:
- Santa Clara CA, US
Gengbin ZHENG - Austin TX, US
Sayantan SUR - Portland OR, US
Maria GARZARAN - Champaign IL, US
Akhil LANGER - Champaign IL, US
International Classification:
G06F 13/16
G06F 16/901
Abstract:
Examples include a computing system having an input/output (I/O) device including a plurality of counters, each counter operating as one of a completion counter and a trigger counter, a processing device; and a memory device. The memory device stores instructions that, in response to execution by the processing device, cause the processing device to represent a plurality of triggered operations of collective communication for high-performance computing executable by the I/O device as a directed acyclic graph stored in the memory device, with triggered operations represented as vertices of the directed acyclic graph and dependencies between triggered operations represented as edges of the directed acyclic graph; traverse the directed acyclic graph using a first process to identify and mark vertices that can share a completion counter; and traverse the directed acyclic graph using a second process to assign a completion counter and a trigger counter for each vertex.

Triggered Operations To Improve Allreduce Overlap

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US Patent:
20190042946, Feb 7, 2019
Filed:
Sep 11, 2018
Appl. No.:
16/127416
Inventors:
- Santa Clara CA, US
James Dinan - Hudson MA, US
Maria Garzaran - Champaign IL, US
Anupama Kurpad - Portland OR, US
Andrew Friedley - Livermore CA, US
Nusrat Islam - Bee Cave TX, US
Robert Zak - Bolton MA, US
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06N 3/08
G06N 3/04
G06N 3/063
Abstract:
An embodiment of a semiconductor package apparatus may include technology to embed one or more trigger operations in one or more messages related to collective operations for a neural network, and issue the one or more messages related to the collective operations to a hardware-based message scheduler in a desired order of execution. Other embodiments are disclosed and claimed.
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Maria J Garzaran from Champaign, IL, age ~56 Get Report