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Margaret A Szymanowski

from Chandler, AZ
Age ~50
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Also known as:
Margaret Szymanowski Living, Margaret A Szmanowski
Phone and address:
782 Powell Way, Chandler, AZ 85249
Connected to:
Charlene A Szymanowski, 73Katarzyna Szymanowska, 53Maciej Szymanowski, 44Paula M Szymanowski, 92Artur Szymanski, 62Dharati L Szymanski, 44Donna Szymanski, 57Doreen T Szymanski, 57Elaine M Szymanski, 80Eric M Szymanski, 47

Margaret Szymanowski Phones & Addresses

  • 782 Powell Way, Chandler, AZ 85249
  • 1091 Kingbird Dr, Chandler, AZ 85248
  • Gilbert, AZ
  • Wichita, KS
  • Maricopa, AZ

Work

Company: Freescale semiconductor Sep 2000 Position: Rf ic design engineering manager

Education

Degree: MSc School / High School: University of Waterloo 1998 to 2000 Specialities: Electrical Engineering

Industries

Semiconductors

Public records

Vehicle Records

Margaret Szymanowski

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Address:
782 E Powell Way, Chandler, AZ 85249
Phone:
(480) 413-6032
VIN:
2HKYF18587H517969
Make:
HONDA
Model:
PILOT
Year:
2007

Resumes

Resumes

Margaret Szymanowski Photo 1

Rfic Design Manager At Freescale Semiconductor

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Position:
RF IC Design Engineering Manager at Freescale Semiconductor
Location:
Phoenix, Arizona Area
Industry:
Semiconductors
Work:
Freescale Semiconductor since Sep 2000
RF IC Design Engineering Manager
Education:
University of Waterloo 1998 - 2000
MSc, Electrical Engineering University of Waterloo 1993 - 1998
BSc, Electrical Engineering

Publications

Us Patents

Electronic Elements And Devices With Trench Under Bond Pad Feature

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US Patent:
8134241, Mar 13, 2012
Filed:
Jul 8, 2011
Appl. No.:
13/179295
Inventors:
Jeffrey K. Jones - Chandler AZ, US
Margaret A. Szymanowski - Chandler AZ, US
Michele L. Miera - Gilbert AZ, US
Xiaowei Ren - Phoenix AZ, US
Wayne R. Burger - Phoenix AZ, US
Mark A. Bennett - Glasgow, GB
Colin Kerr - South Lanarkshire, GB
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 23/48
US Classification:
257786, 257E2159, 257E23023
Abstract:
Electronic elements having an active device region and bonding pad (BP) region on a common substrate desirably include a dielectric region underlying the BP to reduce the parasitic impedance of the BP and its interconnection as the electronic elements are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e. g. , oxide only) dielectric regions can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region having electrically isolated inclusions of a thermal expansion coefficient (TEC) less than that of the dielectric material in which they are embedded and/or closer to the substrate TEC. For silicon substrates, poly or amorphous silicon is suitable for the inclusions and silicon oxide for the dielectric material. The inclusions preferably have a blade-like shape separated by and enclosed within the dielectric material.

Rf Device And Method With Trench Under Bond Pad Feature

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US Patent:
20100140814, Jun 10, 2010
Filed:
Dec 4, 2008
Appl. No.:
12/328319
Inventors:
Jeffrey K. Jones - Chandler AZ, US
Margaret A. Szymanowski - Chandler AZ, US
Michele L. Miera - Gilbert AZ, US
Xiaowei Ren - Phoenix AZ, US
Wayne R. Burger - Phoenix AZ, US
Mark A. Bennett - Glasgow, GB
Colin Kerr - South Lanarkshire, GB
Assignee:
FREESCALE SEMICONDUCTOR, INC. - Austin TX
International Classification:
H01L 21/768
H01L 23/488
US Classification:
257786, 438612, 257E23023, 257E2159
Abstract:
Electronic elements (″) having an active device region () and bonding pad (BP) region () on a common substrate () desirably include a dielectric region underlying the BP () to reduce the parasitic impedance of the BP () and its interconnection () as the electronic elements (″) are scaled to higher power and/or operating frequency. Mechanical stress created by plain (e.g., oxide only) dielectric regions (′) can adversely affect performance, manufacturing yield, pad-to-device proximity and occupied area. This can be avoided by providing a composite dielectric region (″) having electrically isolated inclusions (′) of a thermal expansion coefficient (TEC) less than that of the dielectric material (″) in which they are embedded and/or closer to the substrate () TEC. For silicon substrates (), poly or amorphous silicon is suitable for the inclusions (″) and silicon oxide for the dielectric material (″). The inclusions (″) preferably have a blade-like shape separated by and enclosed within the dielectric material (″).

Digital Step Attenuator And Method For Operating A Digital Step Attenuator

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US Patent:
20210320646, Oct 14, 2021
Filed:
Apr 9, 2020
Appl. No.:
16/844954
Inventors:
- Austin TX, US
Margaret A SZYMANOWSKI - Chandler AZ, US
Chun-Wei CHANG - Chandler AZ, US
International Classification:
H03H 11/24
Abstract:
Embodiments of a digital step attenuator are disclosed. In an embodiment, a digital step attenuator includes a radio frequency (RF) input, an RF output, an attenuation circuit connected between the RF input and the RF output, a shunt switching circuit connected to the attenuator circuit, and a bypass switching circuit connected between the RF input and the RF output. The bypass switching circuit includes a first bypass transistor, and a second bypass transistor, wherein the first bypass transistor and the second bypass transistor are series connected to each other between the RF input and the RF output, and a bypass shunt transistor connected between the first bypass transistor and the second bypass transistor.

Integrated Multiple-Path Power Amplifier

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US Patent:
20200403576, Dec 24, 2020
Filed:
Jun 24, 2019
Appl. No.:
16/449994
Inventors:
- AUSTIN TX, US
Margaret A. Szymanowski - Chandler AZ, US
International Classification:
H03F 1/02
H01L 27/06
H01L 23/528
H01L 23/66
H01L 23/00
H01L 49/02
H01L 27/02
H03F 3/213
H03F 1/56
Abstract:
A multiple-path amplifier (e.g., a Doherty amplifier) includes a first transistor (e.g., a main amplifier FET), a second transistor (e.g., a peaking amplifier FET), a combining node, and a shunt-inductance circuit. The first and second amplifiers and the combining node structure are integrally-formed with a semiconductor die, and the shunt-inductance circuit is integrated with the die. Outputs of the first and second transistors are electrically coupled to the combining node structure. The shunt-inductance circuit is electrically coupled between the combining node structure and a ground reference node. The shunt-inductance circuit includes a shunt inductance (e.g., including wirebond(s) and/or spiral inductor(s)) that is integrated with the semiconductor die. The multiple-path amplifier also may include an integrated phase shifter/impedance inverter coupled between the outputs of the first and second transistors, and which is configured to impart a 90-degree phase delay between intrinsic drains of the first and second transistors.

Power Amplifier With Integrated Bias Circuit Having Multi-Point Input

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US Patent:
20200186096, Jun 11, 2020
Filed:
Nov 15, 2019
Appl. No.:
16/685531
Inventors:
- Austin TX, US
Margaret Szymanowski - Chandler AZ, US
Xin Fu - Chandler AZ, US
International Classification:
H03F 1/02
H03F 3/213
H01L 23/00
H03F 3/21
H01L 23/66
H03F 1/56
Abstract:
A power amplifier includes a semiconductor die, and an amplifier and bias circuit integrally formed with the semiconductor die. The die has opposed first and second sides, and a device bisection line extends between the first and second sides. The bias circuit includes a multi-point input terminal with first and second terminals that are electrically connected through a conductive path that extends across the device bisection line, and one or more bias circuit components connected between the multi-point input terminal and the amplifier. The amplifier may include a field effect transistor (FET) with gate and drain terminals, and the bias circuit component(s) are electrically connected between the multi-point input terminal and the gate terminal. In addition or alternatively, the bias circuit component(s) are electrically connected between a multi-point input terminal and the drain terminal. The one or more components may include a resistor-divider circuit.

Integrally-Formed Multiple-Path Power Amplifier With On-Die Combining Node Structure

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US Patent:
20200186097, Jun 11, 2020
Filed:
Nov 15, 2019
Appl. No.:
16/685666
Inventors:
Margaret Szymanowski - Chandler AZ, US
Xin Fu - Chandler AZ, US
International Classification:
H03F 1/02
H03F 3/21
H01L 23/00
H01L 23/66
H03F 3/213
Abstract:
A multiple-path amplifier (e.g., a Doherty amplifier) includes a semiconductor die, a radio frequency (RF) signal input terminal, a combining node structure integrally formed with the semiconductor die, and first and second amplifiers (e.g., main and peaking amplifiers) integrally formed with the die. Inputs of the first and second amplifiers are electrically coupled to the RF signal input terminal. A plurality of wirebonds is connected between an output of the first amplifier and the combining node structure. An output of the second amplifier is electrically coupled to the combining node structure (e.g., through a conductive path with a negligible phase delay). A phase delay between the outputs of the first and second amplifiers is substantially equal to 90 degrees. The second amplifier may be divided into two amplifier portions that are physically located on opposite sides of the first amplifier.

Power Amplifier Integrated Circuit With Integrated Shunt-L Circuit At Amplifier Output

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US Patent:
20200186107, Jun 11, 2020
Filed:
Feb 19, 2020
Appl. No.:
16/795211
Inventors:
- Austin TX, US
Margaret A. Szymanowski - Chandler AZ, US
International Classification:
H03F 3/195
H03F 3/24
H03F 3/21
H03F 1/56
H03F 1/02
Abstract:
A multiple-path (e.g., Doherty) amplifier includes a semiconductor die, a radio frequency (RF) signal input terminal, a combining node structure integrally formed with the semiconductor die, first and second amplifiers (e.g., main and peaking amplifiers, or vice versa) integrally formed with the semiconductor die, and a shunt circuit electrically connected between an output of the first amplifier and a ground reference node. Inputs of the first and second amplifier are electrically coupled to the RF signal input terminal, and outputs of the first and second amplifier are electrically coupled to the combining node structure. The shunt circuit includes a shunt inductance and a shunt capacitance coupled in series between the output of the first amplifier and the ground reference node, and the shunt capacitance has a first terminal coupled to the shunt inductance, and a second terminal coupled to the ground reference node.

Multiple-Path Rf Amplifiers With Angularly Offset Signal Path Directions, And Methods Of Manufacture Thereof

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US Patent:
20200144968, May 7, 2020
Filed:
Jan 7, 2020
Appl. No.:
16/736443
Inventors:
- Austin TX, US
Margaret A. Szymanowski - Chandler AZ, US
International Classification:
H03F 1/02
H03F 3/24
H03F 3/189
H03F 3/60
H03F 3/213
H03F 3/21
H03F 3/193
H01L 25/00
H01L 25/065
H01L 23/00
H01L 23/66
H01L 23/498
Abstract:
A Doherty amplifier module includes a substrate, an RF signal splitter, a carrier amplifier die, and first and second peaking amplifier dies. The RF signal splitter divides an input RF signal into first, second, and third input RF signals, and conveys the input RF signals to splitter output terminals. The carrier amplifier die includes one or more first power transistors configured to amplify, along a carrier signal path, the first input RF signal to produce an amplified first RF signal. The peaking amplifier dies each include one or more additional power transistors configured to amplify, along first and second peaking signal paths, the second and third input RF signals to produce amplified second and third RF signals. The dies are coupled to the substrate so that the RF signal paths through the carrier and one or more of the peaking amplifier dies extend in substantially different (e.g., orthogonal) directions.
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Margaret A Szymanowski from Chandler, AZ, age ~50 Get Report