Search

Manojkumar Pyla

from San Diego, CA
Age ~47
Get Report
Also known as:
Pyla Manojkumar, R Pyla
Phone and address:
17584 Ralphs Ranch Rd, San Diego, CA 92127
(858) 437-2158
Related to:
Ramalingeshwar Rao PylaLakshmi Sarojini PylaNeelkamal Pyla
Connected to:
Thomas W Pyla, 87Robert E Pylak, 28Ryan Pyland, 35Shawn Pyland, 66Todd B Pyland, 50Brandon J Pylant, 48Cortney L Pylant, 40Josh Pylant, 47Julia J Pylant, 125Katherine D Pylant, 105

Manojkumar Pyla Phones & Addresses

  • 17584 Ralphs Ranch Rd, San Diego, CA 92127 (858) 437-2158
  • 16957 Laurel Hill Ln #207, San Diego, CA 92127
  • 10378 Caminito Alvarez, San Diego, CA 92126 (858) 880-3741
  • 3102 Kings Ct, Raleigh, NC 27606
  • Poway, CA

Work

Company: Qualcomm Aug 2001 Position: Principal engineer

Education

Degree: Master of Science, Masters School / High School: North Carolina State University 1999 to 2001 Specialities: Electrical Engineering

Skills

Asic • Verilog • Soc • Semiconductors • Rtl Design • Ic • Static Timing Analysis • Debugging • Vlsi • Systemverilog • Embedded Systems • Digital Signal Processors • Arm

Languages

Telugu

Industries

Telecommunications

Resumes

Resumes

Manojkumar Pyla Photo 1

Principal Engineer

View page
Location:
3102 Kings Ct, Raleigh, NC 27606
Industry:
Telecommunications
Work:
Qualcomm
Principal Engineer
Education:
North Carolina State University 1999 - 2001
Master of Science, Masters, Electrical Engineering Indian Institute of Technology, Madras 1995 - 1999
Bachelors, Bachelor of Technology, Electrical Engineering
Skills:
Asic
Verilog
Soc
Semiconductors
Rtl Design
Ic
Static Timing Analysis
Debugging
Vlsi
Systemverilog
Embedded Systems
Digital Signal Processors
Arm
Languages:
Telugu

Publications

Us Patents

Embedded Trace Macrocell For Enhanced Digital Signal Processor Debugging Operations

View page
US Patent:
8341604, Dec 25, 2012
Filed:
Nov 15, 2006
Appl. No.:
11/560339
Inventors:
Lucian Codrescu - Austin TX, US
William C. Anderson - Austin TX, US
Suresh Venkumahanti - Austin TX, US
Louis Achille Giannini - Berwyn IL, US
Manojkumar Pyla - San Diego CA, US
Xufeng Chen - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G06F 9/44
US Classification:
717129, 717124, 717125, 717128
Abstract:
Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e. g. , CDMA) system. The method and system improve software instruction debugging operations by capturing real-time information relating to software execution flow and include and instructions and circuitry for operating a core processor process within a core processor. A non-intrusive debugging process operates within a debugging mechanism of a digital signal processor. Non-intrusively monitoring in real time predetermined aspects of software execution occurs with the core processing process and occurs in real-time on the processor. An embedded trace macrocell records selectable aspects of the non-intrusively monitored software execution and generates at least one breakpoint in response to events arising within the selectable aspects of the non-intrusively monitored software execution. The present disclosure controls aspects of the non-intrusive debugging process in response to at least one breakpoint.

Non-Intrusive, Thread-Selective, Debugging Method And System For A Multi-Thread Digital Signal Processor

View page
US Patent:
8370806, Feb 5, 2013
Filed:
Nov 15, 2006
Appl. No.:
11/560217
Inventors:
Lucian Codrescu - Austin TX, US
William C. Anderson - Austin TX, US
Suresh Venkumahanti - Austin TX, US
Louis Achille Giannini - Berwyn IL, US
Manojkumar Pyla - San Diego CA, US
Xufeng Chen - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G06F 9/44
US Classification:
717124, 717129, 714 35
Abstract:
A method and system provide processing instructions in a multi-threaded process including the use of breakpoint instructions for generating debugging event(s). A debugging event is generated in response to the execution of breakpoint instructions and executes debugging instructions in response to the debugging event. The debugging instructions debug processing instructions in the multi-threaded processor by transitioning at least one or more threads into a debugging mode. A debugging return is generated for reporting the executing debugging instructions in the subset of the threads of the multi-threaded processor.

Method And System For Instruction Stuffing Operations During Non-Intrusive Digital Signal Processor Debugging

View page
US Patent:
8380966, Feb 19, 2013
Filed:
Nov 15, 2006
Appl. No.:
11/560344
Inventors:
Lucian Codrescu - Austin TX, US
William C. Anderson - Austin TX, US
Suresh Venkumahanti - Austin TX, US
Louis Achille Giannini - Berwyn IL, US
Manojkumar Pyla - San Diego CA, US
Xufeng Chen - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G06F 11/00
US Classification:
712227, 712 32, 712 38, 714 35
Abstract:
Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e. g. , CDMA) system. Stuffing instructions in a processing pipeline of a multi-threaded digital signal processor provides for operating a core processor process and a debugging process within a debugging mechanism. Writing a stuff instruction into a debugging process registry and a stuff command in a debugging process command register provides for identifying a predetermined thread of the multi-threaded digital signal processor in which to execute the stuff instruction. The instruction stuffing process issues a debugging process control resume command during a predetermined stage of executing on the predetermined thread and directs the core processor to perform the stuff instruction during the debugging process. The core processor may then execute the stuffed instruction in association with the core processor process and the debugging process.

Method And System For Trusted/Untrusted Digital Signal Processor Debugging Operations

View page
US Patent:
8533530, Sep 10, 2013
Filed:
Nov 15, 2006
Appl. No.:
11/560332
Inventors:
Lucian Codrescu - Austin TX, US
William C. Anderson - Austin TX, US
Suresh Venkumahanti - Austin TX, US
Louis Achille Giannini - Berwyn IL, US
Manojkumar Pyla - San Diego CA, US
Xufeng Chen - San Diego CA, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G06F 11/00
US Classification:
714 21, 726 21
Abstract:
Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e. g. , CDMA) system. Trusted and untrusted debugging operational control occurs in operating a core processor associated with the digital signal processor. A debugging process within a debugging mechanism associates with the core processor. The core processor process determines the origin of debugging control as trusted debugging control or untrusted debugging control. In the event of trusted debugging control, the core processor process provides to the trusted debugging control a first set of features and privileges. Alternatively, in the event that debugging control is untrusted debugging control, the core processor process provides the untrusted debugging control a second restricted set of features and privileges, all for maintaining security and proper operation of the core processor process.

Debugging Techniques For A Programmable Integrated Circuit

View page
US Patent:
20080313442, Dec 18, 2008
Filed:
Jun 13, 2007
Appl. No.:
11/762647
Inventors:
Jian Wei - San Diego CA, US
Manojkumar Pyla - San Diego CA, US
Xufeng Chen - San Diego CA, US
International Classification:
G06F 9/30
US Classification:
712227
Abstract:
Techniques for debugging a programmable integrated circuit are described. Embodiments include steps of initiating instruction-cache-misses in the integrated circuit using a remote computer executing a test program; substituting, during an instruction-cache-miss event, instructions in the application program with test instructions provided by the test program; and debugging the integrated circuit based on analysis of its responses to the test instructions. In exemplary applications, such techniques are used for debugging graphics processors of wireless communication system-on-chip devices, among other programmable integrated circuit devices.

Method And Apparatus For Monitoring Interrupts During A Power Down Event At A Processor

View page
US Patent:
20120047402, Feb 23, 2012
Filed:
Aug 23, 2010
Appl. No.:
12/861171
Inventors:
Xufeng Chen - San Diego CA, US
Peixin Zhong - San Diego CA, US
Manojkumar Pyla - San Diego CA, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
G06F 11/00
G06F 13/24
US Classification:
714 3813, 710267, 714E11024, 714 473
Abstract:
In a particular embodiment, a method of monitoring interrupts during a power down event at a processor includes activating an interrupt monitor to detect interrupts. The method also includes isolating an interrupt controller of the processor from the interrupt monitor, where the interrupt controller shares a power domain with the processor. The method also includes detecting interrupts at the interrupt monitor during a power down time period associated with the power down event.

Data Storage For Voltage Domain Crossings

View page
US Patent:
20130039133, Feb 14, 2013
Filed:
Aug 12, 2011
Appl. No.:
13/208450
Inventors:
Christopher Edward Koob - Round Rock TX, US
Jen Tsung Lin - San Diego CA, US
Manojkumar Pyla - San Diego CA, US
Martin Saint-Laurent - Austin TX, US
Assignee:
QUALCOMM INCORPORATED - San Diego CA
International Classification:
G11C 5/14
US Classification:
36518911
Abstract:
According to an embodiment, an apparatus includes a data storage device. Data to be stored in the data storage device is level shifted from a first voltage domain to a second voltage domain prior to being stored within the data storage device. The data storage device is powered by the second voltage domain. The apparatus further includes a circuit that is powered by the second voltage domain and that is responsive to data output by the data storage device.

Dual-Voltage Domain Memory Buffers, And Related Systems And Methods

View page
US Patent:
20130182515, Jul 18, 2013
Filed:
Dec 19, 2012
Appl. No.:
13/719881
Inventors:
Paul D. Bassett - Austin TX, US
Manojkumar Pyla - San Diego CA, US
Robert A. Lester - Austin TX, US
Christopher E. Koob - Austin TX, US
Assignee:
QUALCOMM Incorporated - San Diego CA
International Classification:
G11C 7/10
US Classification:
36518915, 36518905, 36518916
Abstract:
Dual-voltage domain memory buffers, and related systems and methods are disclosed. To reduce area needed for voltage level shifters for voltage level shifting, latch banks are provided in a voltage domain of memory buffer read circuitry, separate from the voltage domain of a write data input to the latch banks. A write data input voltage level shifter is disposed between the write data input and the latch banks to voltage level shift write data on the write data input to the voltage domain of the latch banks. In this manner, voltage level shifters are not required to voltage level shill the latch bank outputs, because the latch banks are in the voltage domain of the memory buffer read circuitry. In this manner, semiconductor area that would otherwise be needed for the voltage level shifters to voltage level shift latch bank outputs is not required.
Control profile
Manojkumar Pyla from San Diego, CA, age ~47 Get Report