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Malcolm Mumme Phones & Addresses

  • Riverside, CA
  • 2801 Tola Ave, Altadena, CA 91001
  • South Pasadena, CA

Work

Company: California baptist university Sep 2017 to Dec 2017 Position: Adjunct instructor

Education

Degree: Doctorates, Doctor of Philosophy School / High School: University of California, Riverside 2009 to 2015 Specialities: Computer Science, Philosophy

Skills

Fortran • Pascal • C++ • Haskell • Actionscript • Java • Parallel Algorithms • Formal Verification • Algorithms • C • Debugging • Digital Signal Processors • Simulations

Interests

Programming • Kayaking • Skating • Physics • Skiing • Logic • Gymnastics • East Coast Swing • Argentine Tango

Industries

Computer Software

Resumes

Resumes

Malcolm Mumme Photo 1

Malcolm Mumme

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Location:
Riverside, CA
Industry:
Computer Software
Work:
California Baptist University Sep 2017 - Dec 2017
Adjunct Instructor

Raytheon Mar 1980 - Oct 1998
Mts

Schick Sunn Classic Pictures Jun 1978 - Sep 1978
Junior Programmer
Education:
University of California, Riverside 2009 - 2015
Doctorates, Doctor of Philosophy, Computer Science, Philosophy
University of California, Riverside 2005 - 2008
Master of Science, Masters, Computer Science
University of California, Riverside 2002 - 2004
Bachelors, Bachelor of Science, Computer Science
Pasadena City College
South Pasadena High School
Skills:
Fortran
Pascal
C++
Haskell
Actionscript
Java
Parallel Algorithms
Formal Verification
Algorithms
C
Debugging
Digital Signal Processors
Simulations
Interests:
Programming
Kayaking
Skating
Physics
Skiing
Logic
Gymnastics
East Coast Swing
Argentine Tango

Publications

Us Patents

Processor Array

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US Patent:
58157280, Sep 29, 1998
Filed:
Mar 1, 1996
Appl. No.:
8/609585
Inventors:
Malcolm A. Mumme - Altadena CA
Assignee:
Raytheon Company - El Segundo CA
International Classification:
G06F 1300
US Classification:
39580001
Abstract:
A processor array 100 having an improved I/O pin utilization scheme. The inventive processor array 100 includes a first and a second set of processors 112 and 114 arranged within a chip boundary B1, with each of the processors 112 within the first set being positioned adjacent the chip boundary B1. The invention further includes an I/O arrangement for providing a plurality of electrical paths 136 across the chip boundary B1. A switch network is included for connecting each of the I/O paths 136 to a horizontal port 130 of an associated one of the processors 112 within the first set during a first clock cycle and for connecting each of the I/O paths 136 to a vertical communication port 132 of the associated processor during a second clock cycle.

Array Of One-Bit Processors Each Having Only One Bit Of Memory

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US Patent:
53794443, Jan 3, 1995
Filed:
Jun 7, 1994
Appl. No.:
8/255294
Inventors:
Malcolm A. Mumme - South Pasadena CA
Assignee:
Hughes Aircraft Company - Los Angeles CA
International Classification:
G06F 1516
US Classification:
395800
Abstract:
A mesh processor array including a plurality of one-bit processor cells arranged in a matrix. Each processor receives inputs from adjacent processors or external sources and performs a logical function involving its own present state and the inputs thereto. Control circuitry provides control information indicative of a logical function to be performed to each of the processors in parallel, and pattern selection circuitry enables selected ones of the processors to respond to the control information.
Malcolm A Mumme from Riverside, CA, age ~64 Get Report