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Majid M Bemanian

from Pleasanton, CA
Age ~61
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Also known as:
Majid N
Phone and address:
17 Foothill Ln, Pleasanton, CA 94588
(925) 417-3405
Related to:
Sohila B Bemanian, 67Marina M Bemanian, 59Ahmad Bemanian, 95Najiz Bemanian, 61Shandis S Bemanian, 28Ghausuddin MatinAmir R Bemanian, 53Edris A Bemanian, 33
Connected to:
Maryam Bemani, 48Lakshmikanth Bemavarapu, 44Christopher D Bemben, 38Amy M Bembenek, 57Ashley J Bembenek, 33Holly M Bembenek, 39Joshua A Bembenek, 32Michele L Bembenek, 69Richard J Bembenek, 58Michelle M Bembenista, 41

Majid Bemanian Phones & Addresses

  • 17 Foothill Ln, Pleasanton, CA 94588 (925) 417-3405
  • Foothill Ln, Pleasanton, CA 94588
  • 43635 Skye Rd, Fremont, CA 94539 (510) 490-7794
  • Tarzana, CA
  • Glendale, CA
  • Van Nuys, CA
  • Alameda, CA
  • 17 Foothill Ln, Pleasanton, CA 94588

Work

Position: Professional/Technical

Education

Degree: Graduate or professional degree

Resumes

Resumes

Majid Bemanian Photo 1

Majid Bemanian

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Applied Micro since Aug 2010
Sr. Director of Marketing
Independant Consultant 2006 - Sep 2010
Executive Consultant
LSI Logic 1995 - 2006
Sr. Director Marketing & Business Development
Raytheon Semiconductor 1994 - 1995
Systems Engineer
Ascom Timeplex 1992 - 1994
Sr. Staff Engineer
Education:
University of Nevada-Reno 1980 - 1984
BS, Electrical Engineering (EE) and minor in Computer Science
Skills:
Embedded Systems
Semiconductors
Product Marketing
Cross Functional Team Leadership
Product Management
Start Ups
Asic
Fpga
Soc
Ic
Majid Bemanian Photo 2

Marketing Director

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Location:
Pleasanton, CA
Industry:
Semiconductors
Work:
Appliedmicro
Marketing Director
Majid Bemanian Photo 3

Marketing Director

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Location:
Pleasanton, CA
Work:
Appliedmicro
Marketing Director

Business Records

Name / Title
Company / Classification
Phones & Addresses
Majid Bemanian
Imaginerium LLC
Consulting · Business Services at Non-Commercial Site
17 Foothill Ln, Pleasanton, CA 94588
1807D Santa Rita Rd, Pleasanton, CA 94566
Majid Bemanian
Director
Tpack Inc
Nonclassifiable Establishments
200 Page Ml Rd, Palo Alto, CA 94306

Publications

Us Patents

Integrated Circuit Having Integrated Programmable Gate Array And Field Programmable Gate Array, And Method Of Operating The Same

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US Patent:
6904586, Jun 7, 2005
Filed:
Mar 25, 2002
Appl. No.:
10/105579
Inventors:
Majid Bemanian - Pleasanton CA, US
William D. Scharf - San Jose CA, US
Bruce L. Entin - Los Gatos CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F017/50
US Classification:
716 16, 716 17, 716 8
Abstract:
An integrated circuit (IC) and a method of manufacturing an integrated circuit suited for a particular application. In one embodiment, the IC includes at least two interfaces, a field-programmable gate array (FPGA) and a programmable gate array (PGA). The FPGA has a configuration memory associated therewith and is coupled to the at least two interfaces for communicating data therebetween. The PGA is coupled to and configured to cooperate with the FPGA to adapt the IC to a particular surrounding environment.

Integrated Circuit Having Integrated Programmable Gate Array And Method Of Operating The Same

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US Patent:
6934597, Aug 23, 2005
Filed:
Mar 26, 2002
Appl. No.:
10/106432
Inventors:
Majid Bemanian - Pleasanton CA, US
William D. Scharf - San Jose CA, US
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G06F019/00
US Classification:
700121, 700 90, 710 52, 710 92, 710 72, 716 16
Abstract:
An integrated circuit (IC) and a method of manufacturing an integrated circuit suited for a particular application. In one embodiment, the IC includes: (1) at least two interfaces, (2) a programmable gate array (PGA) coupled to the at least two interfaces for communicating data therebetween and, optionally (3) a field-programmable gate array (FPGA) coupled to and configured to cooperate with the PGA to adapt the IC to a particular surrounding environment.

Time Division Media Access Controller And Method Of Operation Thereof

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US Patent:
7233604, Jun 19, 2007
Filed:
Jun 4, 2002
Appl. No.:
10/162504
Inventors:
Majid Bemanian - Pleasanton CA, US
Narayanan Raman - Milpitas CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
H04J 3/00
H04L 12/56
US Classification:
370498, 370419, 370420
Abstract:
A time division media access controller for use with a multi-port data switch and a method of controlling media access. In one embodiment, the time division media access controller includes a time division receive engine, a time division transmit engine and a time division arbiter coupled to the time division receive and transmit engines. The time division receive engine accepts data from a plurality of data ports and the time division transmit engine provides data to a plurality of data ports. The time division arbiter controls states of the time division receive and transmit engines based on throughput requirements of the data. In preferred embodiments, the time division media access controller complies with the IEEE 802. 3 ethernet standard.

Flexible Template Having Embedded Gate Array And Composable Memory For Integrated Circuits

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US Patent:
7831653, Nov 9, 2010
Filed:
Dec 13, 2002
Appl. No.:
10/318792
Inventors:
George Wayne Nation - Eyota MN, US
Gary Scott Delp - Rochester MN, US
William D. Scharf - San Jose CA, US
Narayanan Raman - Milpitas CA, US
Majid Bemanian - Pleasanton CA, US
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G06F 15/16
US Classification:
709200, 709230
Abstract:
A partially manufactured semiconductor chip comprising a slice and a number of shells is a template for a communication and networking chip. The slice has a number of I/O ports, blocks, and PHYs. The hardmac PHYs are established to correspond to a high speed data transmission protocol. The interior of the template comprises logic gate arrays and configurable memory. Once particular protocols of data receipt and transmission are selected, the logic gate arrays and configurable memory can be programmed and otherwise configured to develop protocol layers for data networking and communication.

Massively Parallel Interconnect Fabric For Complex Semiconductor Devices

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US Patent:
8390035, Mar 5, 2013
Filed:
May 6, 2009
Appl. No.:
12/436235
Inventors:
Majid Bemanian - Pleasanton CA, US
Farhang Yazdani - Bellevue WA, US
International Classification:
H01L 23/52
US Classification:
257209, 257E29302, 326 38, 326 39, 345530, 438132, 713 1
Abstract:
An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF.

Massively Parallel Interconnect Fabric For Complex Semiconductor Devices

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US Patent:
20120068229, Mar 22, 2012
Filed:
Nov 27, 2011
Appl. No.:
13/304681
Inventors:
Majid Bemanian - Pleasanton CA, US
Farhang Yazdani - Bellevue WA, US
International Classification:
H01L 29/66
US Classification:
257209, 257E29166
Abstract:
An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.

Massively Parallel Interconnect Fabric For Complex Semiconductor Devices

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US Patent:
20120086050, Apr 12, 2012
Filed:
Dec 17, 2011
Appl. No.:
13/329266
Inventors:
Majid Bemanian - Pleasanton CA, US
Farhang Yazdani - Bellevue WA, US
International Classification:
H01L 23/52
US Classification:
257209, 257E23141
Abstract:
An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF.

Method Of Handshaking In A Data Communications Bus

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US Patent:
58570870, Jan 5, 1999
Filed:
Aug 25, 1997
Appl. No.:
8/918091
Inventors:
Majid Bemanian - Fremont CA
John Bailey - Calabassas CA
Assignee:
Timeplex, Inc. - Woodcliff Lake NJ
International Classification:
G06F 1300
US Classification:
395309
Abstract:
A pipelined bus which can support more than one channel between data sources and data destinations at a time. The bus includes an arbitration bus, a command bus and a data bus. In accordance with the bus protocol, different channels may access the various bus components in the same clock cycle. For example, the data source of one channel may issue a command on the command bus to its selected data destination to get ready to receive data while at the same time, a data source of a second channel actually transmits data on the data bus to its selected data destination. During the same clock cycle, a third data source can be selected by the arbitration bus to initiate or resume a channel. In the following clock cycle, the third data source can transmit a command on the command bus to its selected data destination to get ready to receive data, the second data source can transmit data on the data bus to its data destination and a fourth data source can be selected by the arbitration bus to initiate or resume a channel. In this manner, the set up and delivery of data for the different channels overlap in each clock cycle.
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Majid M Bemanian from Pleasanton, CA, age ~61 Get Report