Search

Mai T Maclennan

from Minneapolis, MN
Age ~65
Get Report
Also known as:
Mai T Machennan
Phone and address:
3225 Quinwood Ln N, Minneapolis, MN 55441
(763) 553-1563
Related to:
Stephen A Maclennan, 65
Connected to:
Brent J Maclennan, 50Chad A Maclennan, 46Helen C Maclennan, 82Jeremy W Maclennan, 37Josh Maclennan, 38Louise J Maclennan, 132Natalia Maclennan, 57Neil R Maclennan, 60Scott B Maclennan, 70Steven M Maclennan, 28

Mai Maclennan Phones & Addresses

  • 3225 Quinwood Ln N, Minneapolis, MN 55441 (763) 553-1563
  • Plymouth, MN
  • Minnetonka, MN

Resumes

Resumes

Mai Maclennan Photo 1

Mai Maclennan

View page
Location:
Minneapolis, MN
Industry:
Semiconductors
Mai Maclennan Photo 2

Mai Maclennan

View page
Location:
Minneapolis, MN
Industry:
Nanotechnology
Mai Maclennan Photo 3

Mai Maclennan

View page
Location:
Minneapolis, MN
Industry:
Semiconductors

Publications

Us Patents

Latching Sense Amplifier With Tri-State Output

View page
US Patent:
6642749, Nov 4, 2003
Filed:
Sep 27, 2002
Appl. No.:
10/256752
Inventors:
Sifang Wu - Savage MN
Steven M. Peterson - Eagan MN
Mai T. MacLennan - Plymouth MN
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
G11C 706
US Classification:
327 55, 327 57
Abstract:
A tri-state sense amplifier is provided, which includes an enable input, a latch and an output driver. The latch has first and second complementary inputs and first and second complementary latch outputs, which are gated by the enable input. The output driver includes a data output, a pull-up transistor coupled to the data output and having a control terminal coupled to the first latch output, and a pull-down transistor coupled to the data output and having a control terminal coupled to the second latch output.

Compiled Variable Internal Self Time Memory

View page
US Patent:
20030099128, May 29, 2003
Filed:
Nov 27, 2001
Appl. No.:
09/994517
Inventors:
Steven Peterson - Eagan MN, US
Sifang Wu - Savage MN, US
Mai MacLennan - Plymouth MN, US
Carl Monzel - Lakeville MN, US
International Classification:
G11C011/00
US Classification:
365/151000
Abstract:
A method for changing the internal timing of a memory to allow adjustment of the access time of the memory to be faster or slower by increasing or decreasing internal margins of the memory (bit line separation), respectively, utilizes the memory compiler for setting the number of core cells used for driving a self time column of the memory.

Read-Only Memory With Complementary Data Lines

View page
US Patent:
53093895, May 3, 1994
Filed:
Aug 27, 1993
Appl. No.:
8/112485
Inventors:
Keith W. Golke - Minneapolis MN
Mai T. MacLennan - Plymouth MN
Assignee:
Honeywell Inc. - Minneapolis MN
International Classification:
G11C 1712
US Classification:
365104
Abstract:
A plurality of single transistor memory cells arrayed in columns with the memory cells within a column connected to one or the other of precharged first and second output lines. An input line connected to the gate of the single transistor causes the first output line to be pulled to a first voltage when the cell is programmed a "true" and to be pulled to a second voltage when the cell is programmed a "complement". A pair of cross-coupled transistors connected between the first and second output lines of a column cause the second output line to be maintained at the precharged voltage when programmed a "true" and causes the first output line to be maintained at a precharged voltage when programmed a "complement".
Control profile
Mai T Maclennan from Minneapolis, MN, age ~65 Get Report