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Mahesh K Sanganeria

from Layton, UT
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Related to:
Kavita SanganeriaAnju Gaur, 50Suresh SanganeriaPunit SanganeriaAnusuya P Gaur, 50
Connected to:
Chetan J Sangani, 45Deepa Sangani, 56Ekta K Sangani, 39Jyoti J Sangani, 48Kajal P Sangani, 39Kalpesh N Sangani, 42Pooja N Sangani, 33Suresh K Sangani, 74Vishal V Sangani, 41Mamadou Sangare, 61

Mahesh Sanganeria Phones & Addresses

  • 3489 Clinton Ave, Santa Clara, CA 95051
  • Layton, UT
  • 1606 Peacock Ave, Sunnyvale, CA 94087 (408) 773-8509
  • 395 Ano Nuevo Ave APT 612, Sunnyvale, CA 94085

Languages

English

Emails

m***[email protected]

Resumes

Resumes

Mahesh Sanganeria Photo 1

Mahesh Sanganeria

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Location:
3489 Clinton Ave, Santa Clara, CA 95051
Languages:
English

Publications

Us Patents

Method Of Controlling Fsg Deposition Rate In An Hdp Reactor

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US Patent:
6403501, Jun 11, 2002
Filed:
Dec 27, 2000
Appl. No.:
09/748991
Inventors:
Jonathan W. Hander - Texas City TX
Mahesh K. Sanganeria - Sunnyvale CA
Julian J. Hsieh - Pleasanton CA
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
H01L 2131
US Classification:
438783, 438784, 438788
Abstract:
A method is provided that conditions the chamber walls of a HDP CVD reactor by forming a layer of doped material prior to depositing dielectric layers of the doped material onto wafers. A consistent deposition rate can be maintained during subsequent deposition. When deposition is halted, the chamber is cleaned and a thin layer of the doped material is formed on the walls. Consequently, the chamber is kept at equilibrium even during periods of idle, thereby allowing the deposition rates to be consistent even after deposition resumes after the idle periods. For prolonged idle times, the chamber is re-cleaned and the doped material is re-deposited periodically, such as every 12 hours.

Method Of Improving Adhesion Between Two Dielectric Films

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US Patent:
6972252, Dec 6, 2005
Filed:
Aug 25, 2003
Appl. No.:
10/647773
Inventors:
Mahesh Sanganeria - Sunnyvale CA, US
Bart van Schravendijk - Sunnyvale CA, US
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
H01L021/44
US Classification:
438624, 438675, 438677, 438902
Abstract:
A method of improving adhesion between layers in the formation of a semiconductor device and integrated circuit, and the resultant intermediate semiconductor structure, which include a substrate layer with a low k insulating layer thereover. The low k insulating layer includes a treated surface area of adsorbed gaseous particles. This treated surface area is formed by flowing a gas, preferably, silane, disilane, dichlorosilane, germane or combinations thereof, over a surface of the heated low k insulating layer for adsorption of such gaseous particles onto the heated surface, wherein the insulating layer maintains its original thickness. A capping layer is then deposited directly over the insulating layer wherein the treated surface area of the insulating layer significantly improves adhesion between the insulating layers and the capping layers to prevent delamination therebetween during subsequent processing steps of forming the integrated circuit.

Protection Of Cu Damascene Interconnects By Formation Of A Self-Aligned Buffer Layer

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US Patent:
7396759, Jul 8, 2008
Filed:
Nov 3, 2004
Appl. No.:
10/980076
Inventors:
Bart van Schravendijk - Sunnyvale CA, US
Thomas W Mountsier - San Jose CA, US
Mahesh K Sanganeria - Sunnyvale CA, US
Glenn B Alers - Scots Valley CA, US
Roey Shaviv - Palo Alto CA, US
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
H01L 21/4763
US Classification:
438625, 438627, 438687, 257E21575
Abstract:
Methods of protecting exposed metal damascene interconnect surfaces in a process for making electronic components and the electronic components made according to such methods. An integrated circuit structure having damascene regions with exposed metal surfaces is provided into a closed processing chamber, whereby a first reactant is contacted to the exposed metal surfaces to transform a top portion of the metal layer into a protective self-aligned buffer layer. Reacting molecules of the first reactant with metal atoms of this metal layer forms the protective self-aligned buffer layer entirely within such metal layer. Alternatively, adsorbing surface-active reactant molecules onto the exposed metal surface forms the protective self-aligned buffer layer. A second reactant may be contacted to the protective self-aligned buffer layer to form a self-aligned dielectric cap layer directly over the protective self-aligned buffer layer.

Method Of Improving Adhesion Between Two Dielectric Films

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US Patent:
7622380, Nov 24, 2009
Filed:
Oct 6, 2005
Appl. No.:
11/245227
Inventors:
Mahesh Sanganeria - Sunnyvale CA, US
Bart van Schravendijk - Sunnyvale CA, US
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
H01L 21/44
US Classification:
438624, 438675, 438677
Abstract:
A method of improving adhesion between layers in the formation of a semiconductor device and integrated circuit, and the resultant intermediate semiconductor structure, which include a substrate layer with a low k insulating layer thereover. The low k insulating layer includes a treated surface area of adsorbed gaseous particles. This treated surface area is formed by flowing a gas, preferably, silane, disilane, dichlorosilane, germane or combinations thereof, over a surface of the heated low k insulating layer for adsorption of such gaseous particles onto the heated surface, wherein the insulating layer maintains its original thickness. A capping layer is then deposited directly over the insulating layer wherein the treated surface area of the insulating layer significantly improves adhesion between the insulating layers and the capping layers to prevent delamination therebetween during subsequent processing steps of forming the integrated circuit.

Method Of Improving Adhesion Between Two Dielectric Films

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US Patent:
7705431, Apr 27, 2010
Filed:
Apr 1, 2008
Appl. No.:
12/060344
Inventors:
Mahesh Sanganeria - Sunnyvale CA, US
Bart van Schravendijk - Sunnyvale CA, US
Assignee:
Novellius Systems, Inc. - San Jose CA
International Classification:
H01L 21/44
US Classification:
257624, 438675, 438677
Abstract:
A method of improving adhesion between layers in the formation of a semiconductor device and integrated circuit, and the resultant intermediate semiconductor structure, which include a substrate layer with a low k insulating layer thereover. The low k insulating layer includes a treated surface area of adsorbed gaseous particles. This treated surface area is formed by flowing a gas, preferably, silane, disilane, dichlorosilane, germane or combinations thereof, over a surface of the heated low k insulating layer for adsorption of such gaseous particles onto the heated surface, wherein the insulating layer maintains its original thickness. A capping layer is then deposited directly over the insulating layer wherein the treated surface area of the insulating layer significantly improves adhesion between the insulating layers and the capping layers to prevent delamination therebetween during subsequent processing steps of forming the integrated circuit.

Protection Of Cu Damascene Interconnects By Formation Of A Self-Aligned Buffer Layer

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US Patent:
8030777, Oct 4, 2011
Filed:
Feb 5, 2007
Appl. No.:
11/671161
Inventors:
Bart van Schravendijk - Sunnyvale CA, US
Thomas W Mountsier - San Jose CA, US
Mahesh K Sanganeria - Sunnyvale CA, US
Glenn B Alers - Scots Valley CA, US
Roey Shaviv - Palo Alto CA, US
Assignee:
Novellus Systems, Inc. - San Jose CA
International Classification:
H01L 23/48
US Classification:
257762, 257768, 257E21199, 257E32157, 438622
Abstract:
Methods of protecting exposed metal damascene interconnect surfaces in a process for making electronic components and the electronic components made according to such methods. An integrated circuit structure having damascene regions with exposed metal surfaces is provided into a closed processing chamber, whereby a first reactant is contacted to the exposed metal surfaces to transform a top portion of the metal layer into a protective self-aligned buffer layer. Reacting molecules of the first reactant with metal atoms of this metal layer forms the protective self-aligned buffer layer entirely within such metal layer. Alternatively, adsorbing surface-active reactant molecules onto the exposed metal surface forms the protective self-aligned buffer layer. A second reactant may be contacted to the protective self-aligned buffer layer to form a self-aligned dielectric cap layer directly over the protective self-aligned buffer layer.

Gas Injection System For Cvd Reactors

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US Patent:
56538081, Aug 5, 1997
Filed:
Aug 7, 1996
Appl. No.:
8/693721
Inventors:
Joseph H. MacLeish - San Ramon CA
Robert D. Mailho - Sonora CA
Mahesh K. Sanganeria - Sunnyvale CA
International Classification:
C23C 1600
US Classification:
118715
Abstract:
A CVD reactor includes separate reaction and pressure chambers, where the reaction chamber is contained within and isolates reactant gases from the pressure chamber. The reactor also includes a gas injection system which injects process gas(es) into the reaction chamber in a somewhat vertical direction through a bottom surface of the reaction chamber. The gas injection system injects hydrogen or other appropriate gas in a vertical direction through the bottom surface of the reaction chamber. The flow of hydrogen or other appropriate gas is intermediate the flow of the process gas(es) and a surface of the reaction chamber, thereby re-directing the process gas flow parallel to the top surface of a wafer therein. In this manner, the reaction chamber does not require a long entry length for the process gas(es). This flow of hydrogen or other suitable gas also minimizes undesirable deposition on the surface of the reaction chamber.

Process For Making Integrated Circuit Structure Comprising Local Area Interconnects Formed Over Semiconductor Substrate By Selective Deposition On Seed Layer In Patterned Trench

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US Patent:
56704259, Sep 23, 1997
Filed:
Nov 9, 1995
Appl. No.:
8/552461
Inventors:
Richard Schinella - Saratoga CA
Mahesh K. Sanganeria - Sunnyvale CA
Assignee:
LSI Logic Corporation - Milpitas CA
International Classification:
H01L 21441
US Classification:
437195
Abstract:
A local area interconnect structure comprising one or more electrically conductive interconnects formed from electrically conductive metal compounds is described and a process for forming same. Electrically conductive metal compounds are selectively deposited in one or more trenches which were previously formed in an insulation layer in a configuration conforming to the desired pattern of the electrically conductive interconnects. A seed layer is first selectively formed on surfaces of the trenches and the electrically conductive metal compound is then selectively deposited over the seed layer in the trench, but not on the exposed surfaces of the insulation layer.
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Mahesh K Sanganeria from Layton, UT Get Report