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Mahbub B Rashed

from Cupertino, CA
Age ~58
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Also known as:
Mahbub Bin Rashed, Mahbub Rownak Rashed, Mahbub M Rashed, Bin Dr Rashed, Bin Rashed Mahbub, Mahbub B Zaman, Mahbub R Zaman, Rashed Mahbub, Mahboub Rached
Phone and address:
18674 Loree Ave, Cupertino, CA 95014
(512) 698-2161
Related to:
M ZamanJose Fernandez, 43Nicole A Roa, 44
Connected to:
Ahmed Rashed, 69Arash Rashed, 48Haitham M Rashed, 47Mai M Rashed, 38Offie T Rashed, 55Raymond N Rashed, 79Salwa R Rashed, 65Saudia N Rashed, 47Mohammad A Rashedi, 43Aalayah Rasheed, 40

Mahbub Rashed Phones & Addresses

  • 18674 Loree Ave, Cupertino, CA 95014 (512) 698-2161
  • 3575 Lehigh Dr, Santa Clara, CA 95051 (408) 564-5486
  • 8405 Axis Dr, Austin, TX 78749
  • 203 39Th St, Austin, TX 78751
  • 104 38Th 1/2 St, Austin, TX 78751
  • Los Alamos, NM
  • 18674 Loree Ave, Cupertino, CA 95014

Work

Company: Cypress semiconductor corporation Oct 2007 to Dec 2009 Position: Director, memory division

Education

Degree: Doctorates, Doctor of Philosophy School / High School: The University of Texas at Austin 1993 to 1996 Specialities: Engineering

Skills

Cmos • Semiconductors • Vlsi • Ic • Integrated Circuit Design • Soc • Asic • Mixed Signal • Wireless • Silicon • Physical Design • Eda • Simulations • Circuit Design • Low Power Design • Architecture • Physics • Semiconductor Industry • Microprocessors • Integrated Circuits • Spice • Device Physics • Verilog • Analog • Debugging • Cadence Virtuoso • Functional Verification • Microelectronics • Product Engineering • Analog Circuit Design • Sram • Drc • Wireless Technologies • Application Specific Integrated Circuits • Very Large Scale Integration • People Skills • Pll • Rtl Design • System on A Chip • Processors

Industries

Semiconductors

Resumes

Resumes

Mahbub Rashed Photo 1

Fellow And Head, Design And Technology Co-Optimization Group

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Location:
Santa Clara, CA
Industry:
Semiconductors
Work:
Cypress Semiconductor Corporation Oct 2007 - Dec 2009
Director, Memory Division
Globalfoundries Oct 2007 - Dec 2009
Fellow and Head, Design and Technology Co-Optimization Group
Freescale Semiconductor Apr 2004 - Sep 2007
Design Service Manager
Motorola Jan 2002 - Mar 2004
Distinguished Member of Technical Staff, Wireless Group
Motorola Jan 2000 - Dec 2002
Principal Eng., Wireless Group
Education:
The University of Texas at Austin 1993 - 1996
Doctorates, Doctor of Philosophy, Engineering The University of Texas at Austin 1992 - 1993
Master of Science, Masters, Engineering Bangladesh University of Engineering and Technology 1986 - 1991
Bachelors, Bachelor of Science, Engineering
Skills:
Cmos
Semiconductors
Vlsi
Ic
Integrated Circuit Design
Soc
Asic
Mixed Signal
Wireless
Silicon
Physical Design
Eda
Simulations
Circuit Design
Low Power Design
Architecture
Physics
Semiconductor Industry
Microprocessors
Integrated Circuits
Spice
Device Physics
Verilog
Analog
Debugging
Cadence Virtuoso
Functional Verification
Microelectronics
Product Engineering
Analog Circuit Design
Sram
Drc
Wireless Technologies
Application Specific Integrated Circuits
Very Large Scale Integration
People Skills
Pll
Rtl Design
System on A Chip
Processors

Publications

Us Patents

System, Method And Program Product For Well-Bias Set Point Adjustment

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US Patent:
7274247, Sep 25, 2007
Filed:
Apr 4, 2005
Appl. No.:
11/098344
Inventors:
Gregory H. Ward - Georgetown TX, US
Mohamed S. Moosa - Round Rock TX, US
Mahbub M. Rashed - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G05F 1/10
US Classification:
327534
Abstract:
A well-bias system dynamically adjusts well-bias set points to optimal levels across an integrated circuit (IC) for enhanced power savings and component reliability during a standby or low-power mode of operation. A controller within the IC determines if the chip power supply voltage will be reduced during an imminent standby or low power mode and sets a register controlling a negative well-bias set point for asserting well-bias to charge wells of the IC accordingly. To minimize leakage current without compromising reliability, the well-bias set point is set to (1) an optimal well-bias set point if a reduced supply voltage is to be applied to the IC, or (2) a minimum well-bias set point when a nominal or high supply voltage is to be applied to the IC.

Programmable Bias For A Memory Array

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US Patent:
7542360, Jun 2, 2009
Filed:
Jul 19, 2007
Appl. No.:
11/780251
Inventors:
Mahbub M. Rashed - Austin TX, US
Robert E. Booth - Austin TX, US
Sushama Davar - Austin TX, US
Giri Nallapati - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
G11C 7/00
US Classification:
365201, 36518525, 36518518, 36518909, 3652257
Abstract:
A method determines a body bias for a memory cell. A supply voltage is applied to the memory cell and a bit line is precharged to a voltage lower than the supply voltage. A programmable bias voltage circuit provides a bias voltage to the memory cell in response to values on its input. Initial test values for the input are used. The memory cell is tested to determine a pass or a fail condition of the memory cell. The initial values are retained as the input values if the memory cell passes. If the memory cell fails, the memory cell is tested at changed values for the input. If the changed input values result in the memory cell being in a pass condition, the programmable bias voltage circuit is configured, in non-volatile fashion, to have the changed input values.

Speedpath Repair In An Integrated Circuit

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US Patent:
7612577, Nov 3, 2009
Filed:
Jul 27, 2007
Appl. No.:
11/829153
Inventors:
Mahbub M. Rashed - Austin TX, US
Milind P. Padhye - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H03K 19/003
US Classification:
326 10, 326 95
Abstract:
A circuit comprises a first plurality of transistors of a first channel length disposed along a speedpath, the first plurality of transistors providing a first timing performance. The circuit also comprises a second plurality of transistors of a second channel length having an expected equivalent functionality as the first plurality of transistors and disposed in parallel with the first plurality of transistors along the speedpath, wherein the second channel length is different from the first channel length. In addition, the circuit comprises an element configured to selectively replace the first plurality of transistors with the second plurality of transistors in response to a determination that the first timing performance of the first plurality of transistors fails a timing requirement of the speedpath. In one embodiment, the second channel length is a sub-minimal geometry with respect to the first channel length.

Method Of Stimulating Die Circuitry And Structure Therefor

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US Patent:
7741195, Jun 22, 2010
Filed:
May 26, 2006
Appl. No.:
11/420551
Inventors:
Mohammed K. Rashid - Austin TX, US
Mahbub M. Rashed - Austin TX, US
Scott S. Roth - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 21/00
US Classification:
438462, 438460, 257E21523, 257E21524
Abstract:
A method includes providing a wafer having a first die and a scribe grid, where the first die has die circuitry and a bond pad electrically connected to the die circuitry, and where the scribe grid has a scribe grid pad electrically connected to the die circuitry. The method further includes accessing the scribe grid pad to stimulate the die circuitry. A wafer includes a first die. The first die includes die circuitry, a plurality of conductive layers, and a bond pad electrically connected to the die circuitry via at least one conductive layer of the plurality of conductive layers. The wafer includes a scribe grid having a scribe grid pad, and an interconnect electrically connecting the scribe grid pad to the die circuitry. The plurality of die of the wafer can then be singulated, and at least one of the singulated die can be packaged.

Hybrid Transistor Based Power Gating Switch Circuit And Method

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US Patent:
7867858, Jan 11, 2011
Filed:
Mar 31, 2008
Appl. No.:
12/059006
Inventors:
Giri Nallapati - Austin TX, US
Sushama Davar - Austin TX, US
Robert E. Booth - Austin TX, US
Michael P. Woo - Austin TX, US
Mahbub M. Rashed - Austin TX, US
Assignee:
Freescale Semiconductor, Inc. - Austin TX
International Classification:
H01L 21/8234
US Classification:
438275, 438276, 438301, 326 33, 326121, 257E21616
Abstract:
A method includes forming a first transistor having a first gate dielectric thickness and a first source/drain extension depth, a second transistor having a second gate dielectric thickness and the first source/drain extension depth, and a third transistor having the second gate dielectric thickness and a second source/drain extension depth. The second source/drain extension depth is greater than the first source/drain extension depth. The second gate dielectric thickness is greater than the first gate dielectric thickness. The first transistor is used in a logic circuit. The third transistor is used in an I/O circuit. The second transistor is made without extra processing steps and is better than either the first or third transistor for coupling a power supply terminal to the logic circuit in a power-up mode and decoupling the power supply terminal from the logic circuit in a power-down mode.

Semiconductor Device With Transistor Local Interconnects

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US Patent:
8581348, Nov 12, 2013
Filed:
Dec 13, 2011
Appl. No.:
13/324699
Inventors:
Mahbub Rashed - Santa Clara CA, US
Steven Soss - Cornwall NY, US
Jongwook Kye - Pleasanton CA, US
Irene Y. Lin - Los Altos Hills CA, US
James Benjamin Gullette - Wadesboro NC, US
Chinh Nguyen - Austin TX, US
Jeff Kim - San Jose CA, US
Marc Tarabbia - Pleasant Valley NY, US
Yuansheng Ma - Santa Clara CA, US
Yunfei Deng - Sunnyvale CA, US
Rod Augur - Hopewell Junction NY, US
Seung-Hyun Rhee - Fishkill NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US
Assignee:
GLOBALFOUNDRIES, Inc. - Grand Cayman
International Classification:
H01L 27/088
H01L 21/70
H01L 21/02
US Classification:
257401, 257368, 257369, 257382, 257384
Abstract:
A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors includes a source, a drain, and a gate. A CA layer is electrically connected to at least one of the source or the drain of the first transistor. A CB layer is electrically connected to at least one of the gates of the transistors and the CA layer.

Semiconductor Device Having Contact Layer Providing Electrical Connections

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US Patent:
8598633, Dec 3, 2013
Filed:
Jan 16, 2012
Appl. No.:
13/351101
Inventors:
Marc Tarabbia - Pleasant Valley NY, US
James B. Gullette - Dresden, DE
Mahbub Rashed - Santa Clara CA, US
David S. Doman - Austin TX, US
Irene Y. Lin - Los Altos Hills CA, US
Ingolf Lorenz - Ottendorf-Okrilla, DE
Larry Ho - Cupertino CA, US
Chinh Nguyen - Austin TX, US
Jeff Kim - San Jose CA, US
Jongwook Kye - Pleasanton CA, US
Yuansheng Ma - Santa Clara CA, US
Yunfei Deng - Sunnyvale CA, US
Rod Augur - Hopewell Junction NY, US
Seung-Hyun Rhee - Fishkill NY, US
Jason E. Stephens - Beacon NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US
Assignee:
GLOBALFOUNDRIES, Inc. - Grand Cayman
International Classification:
H01L 23/52
US Classification:
257207, 257211
Abstract:
A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor.

Semiconductor Devices Formed On A Continuous Active Region With An Isolating Conductive Structure Positioned Between Such Semiconductor Devices, And Methods Of Making Same

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US Patent:
8618607, Dec 31, 2013
Filed:
Jul 2, 2012
Appl. No.:
13/539830
Inventors:
Mahbub Rashed - Santa Clara CA, US
David Doman - Austin TX, US
Marc Tarabbia - Pleasant Valley NY, US
Irene Lin - Los Altos Hills CA, US
Jeff Kim - San Jose CA, US
Chinh Nguyen - Austin TX, US
Steve Soss - Cornwall NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Malta NY, US
Assignee:
GLOBALFOUNDRIES Inc. - Grand Cayman
International Classification:
H01L 21/02
US Classification:
257359, 257369, 257379, 257E21602, 257E21656, 257E23144, 257E23152, 257E27029, 257E27081, 257E29226, 257E29276
Abstract:
One illustrative device disclosed herein includes a continuous active region defined in a semiconducting substrate, first and second transistors formed in and above the continuous active region, each of the first and second transistors comprising a plurality of doped regions formed in the continuous active region, a conductive isolating electrode positioned above the continuous active region between the first and second transistors and a power rail conductively coupled to the conductive isolating electrode.
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Mahbub B Rashed from Cupertino, CA, age ~58 Get Report