Mahadevamurty M Nemani

6631444, Oct 7, 2003

Jun 27, 2001

09/894513

Kenneth R. Smits - San Ramon CA
Bharat Bhushan - Cupertino CA
Mahadevamurty Nemani - Sunnyvale CA

Intel Corporation - Santa Clara CA

G06F 1208

711118, 711169, 711167, 711140, 365 51

Architecture for a cache fabricated on a die with a processor including a plurality of cache banks, each containing a plurality of storage cell subarrays, the cache banks being arranged in physical relationship to a central location on the die that provides a point for information transfer between the processor and the cache. A data path provides synchronous transmission of data to/from the cache banks such that data requested by the processor in a given clock cycle is received at the central location a predetermined number of clock cycles later regardless of which cache bank in the cache the data is stored.

6922798, Jul 26, 2005

Jul 31, 2002

10/210342

Mahadevamurty Nemani - Sunnyvale CA, US
Kenneth R. Smits - San Ramon CA, US

Intel Corporation - Santa Clara CA

G11C031/28

714710, 714711

Apparatus and methods for providing enhanced redundancy for a cache are provided. For example, an on-die cache is disclosed which includes a first memory array having a defective array line; a second memory array having a defective array line; and a redundant memory array having a plurality of array lines. A first one of the array lines is mapped to the defective array line of the first array and a second one of the array lines is mapped to the defective array line of the second array.

7164616, Jan 16, 2007

Dec 20, 2004

11/018013

Jeffrey L. Miller - Vancouver WA, US
Mahadevamurty Nemani - Hillsboro OR, US
James W. Conary - Beaverton OR, US

Intel Corporation - Santa Clara CA

G11C 8/00

36523006, 365226, 365227, 365228, 365229, 365154, 326 83

Disclosed herein are techniques for reducing standby power consumption due to leakage currents in memory array circuits.

7345947, Mar 18, 2008

Sep 5, 2006

11/516209

Jeffrey L. Miller - Vancouver WA, US
Mahadevamurty Nemani - Hillsboro OR, US
James W. Conary - Beaverton OR, US

Intel Corporation - Santa Clara CA

G11C 8/00

36523006, 365226, 365227, 365228, 365229

Embodiments of the invention provide techniques for reducing standby power consumption due to leakage currents in memory circuits. In some embodiments, systems are provided with one or more processors having) bit cells coupled to a word-line node and to a virtual ground node. The word-line node is to be at an active word-line voltage when the row is active and an inactive word-line voltage when the row is inactive. The virtual ground node is to be at an operational ground voltage when the memory array is enabled and at an elevated voltage when the memory array is in a standby mode. There is also a word-line driver circuit coupled to the bit cells through the word-line and virtual ground nodes. The current leakage in the bit cells and word-line driver circuit is reduced during the standby mode when the virtual ground node is at the elevated voltage.

6327552, Dec 4, 2001

Dec 28, 1999

9/474008

Mahadevamurty Nemani - Sunnyvale CA
Franklin Baez - San Jose CA

Intel Corporation - Santa Clara CA

G06F 1518

703 2

A method, system and computer program product for automatically determining optimal design parameters of a subsystem to meet design constraints. The subsystem comprises a plurality of circuits. The optimal design parameters are determined by performing a parameter-delay curve optimization of the subsystem design parameters. Specifically, an embodiment of the present invention provides a method and/or computer program product for determining optimal values for the design parameters of a circuit block, which result in optimally assigned delay targets for datapath blocks at the minimum power/area point. The problem/solution space is extended to solve the problem of figuring out the best possible implementation, for example, static vs dynamic, for each datapath block. Based on parameter functions, which relate to the design parameters for circuits in the circuit block, the design parameters are optimized to satisfy the design constraints. In one embodiment, the design parameters include power and delay and the parameter functions are power-delay curves.

61114359, Aug 29, 2000

Jun 30, 1999

9/343961

Jiann-Cherng James Lan - San Jose CA
Mahadevamurty Nemani - Sunnyvale CA
Narsing K. Vijayrao - Santa Clara CA
Wenjie Jiang - Sunnyvale CA
Sudarshan Kumar - Fremont CA

Intel Corporation - Santa Clara CA

H03K 1920

326121

A circuit includes first and second pull-up transistors having first and second drains, respectively, each coupled to separate voltage clamps. The gates of each of the two pull-up transistors are coupled to a clock signal line. The circuit further includes a shared pull-down transistor, the gate of which is coupled to the clock signal line. The drain of the shared pull-down transistor is coupled to the first drain via at least one pull-down transistor in series with the shared pull-down transistor. The drain of the shared pull-down transistor is also coupled to the second drain via at least one pull-down transistor in series with the shared pull-down transistor. This circuit may be found useful in multiplexing applications.

20210397714, Dec 23, 2021

Jun 17, 2020

16/903982

- SAN DIEGO CA, US
Samar ASBE - San Diego CA, US
Miguel BALLESTEROS - San Diego CA, US
Girish BHAT - San Diego CA, US
Mahadevamurty NEMANI - San Diego CA, US

G06F 21/57
G06F 9/445
G06F 9/50
G06F 21/62

Resource access control in a system-on-chip (“SoC”) may employ an agent executing on a processor of the SoC and a trust management engine of the SoC. The agent, such as, for example, a high-level operating system or a hypervisor, may be configured to allocate a resource comprising a memory region to an access domain and to load a software image associated with the access domain into the memory region. The trust management engine may be configured to lock the resource against access by any entity other than the access domain, to authenticate the software image associated with the access domain, and to initiate booting of the access domain in response to a successful authentication of the software image associated with the access domain.

20210365557, Nov 25, 2021

May 21, 2020

16/880819

- San Diego CA, US
Miguel BALLESTEROS - Solana Beach CA, US
Mahadevamurty NEMANI - San Diego CA, US
Samar ASBE - San Diego CA, US
Girish BHAT - San Diego CA, US
Alan YOUNG - Carlsbad CA, US
Victor WONG - San Diego CA, US
Steven HALTER - San Diego CA, US

G06F 21/57
G06F 21/44
G06F 11/36
G06F 13/42

A method for external access control to protect system-on-chip (SoC) subsystems and stored subsystem assets is described. The method includes sensing, during a cold boot of an SoC hardware system, a debug fuse vector for access to SoC subsystems of an SoC owner and/or third-party subsystems of an SoC hardware architecture. The method also includes disabling access to each SoC subsystem with a blown fuse in the debug fuse vector. The method further includes re-enabling, by a secure root of trust, access to an SoC subsystem and/or a third-party subsystem for an external debugger when authentication of one or more debug certificates of a third-party owner of the external debugger is successful.