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Lonnie R Heidtke

from Chippewa Falls, WI
Age ~75
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Also known as:
Lonnie R Hedtke, Lonnier R Heidtke, Lonnie R Heidke, Lonnie Haedtke, Lonnie Heike
Related to:
Anna HeidtkeE PernellMehrdad JalilpourJames Pernell, 59Jalil Jalilpour, 92Esfahani K Jalilpour, 66
Connected to:
Richard E Heidtke, 57Richard J Heidtman, 45Linda K Heidy, 75Jonathan D Heie, 52Aaron W Heien, 49Gary D Heien, 61Kimberly C Heien, 55Roger L Heien, 65William W Heiens, 90Christopher J Heier, 44

Lonnie Heidtke Phones & Addresses

  • Chippewa Falls, WI
  • Winter, WI
  • 1305 River Ave E, Ladysmith, WI 54848 (715) 382-4682
  • 11512 161St St, Chippewa Falls, WI 54729 (715) 382-4682
  • 10090 County Hwy, Chippewa Falls, WI 54729 (715) 720-6076
  • Hudson, WI
  • 10090 County Hwy N, Chippewa Falls, WI 54729 (715) 382-4682

Work

Position: Technicians and Related Support Occupations

Education

Degree: High school graduate or higher

Awards

Us patents

Emails

k***[email protected]

Industries

Computer Hardware

Resumes

Resumes

Lonnie Heidtke Photo 1

Lonnie Heidtke

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Location:
Eau Claire, Wisconsin Area
Industry:
Computer Hardware
Awards:
US Patents
US Patent 4,951,246 - Nibble-mode dram solid state storage device US Patent 5,321,697 - Solid state storage device US Patent 5,388,217 - Distributing system for multi-processor input and output using channel adapters

Business Records

Name / Title
Company / Classification
Phones & Addresses
Lonnie Heidtke
Director Program Management, Design Services
Open-Silicon, Inc
Custom Computer Programing Engineering Services Mfg Semiconductors/Related Devices
7 S Dewey St, Eau Claire, WI 54701
(715) 830-1200

Publications

Us Patents

Distributing System For Multi-Processor Input And Output Using Channel Adapters

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US Patent:
53882172, Feb 7, 1995
Filed:
Dec 13, 1991
Appl. No.:
7/807082
Inventors:
Gary E. Benzschawel - Chippewa Falls WI
Lonnie R. Heidtke - Chippewa Falls WI
Steven S. Chen - Chippewa Falls WI
Fredrich J. Simmons - Eau Claire WI
George A. Spix - Eau Claire WI
Assignee:
Cray Research, Inc. - Eagan MN
International Classification:
G06F 1516
US Classification:
395275
Abstract:
Four clusters of 16 CPU's each are each associated with a solid state memory and a main memory. Each CPU is uniquely associated with a channel arbitrator which interconnects the associated CPU to serial ports. Each channel arbitrator is associated with a set of 16 serial channels. Each serial channel is in turn interconnected to a channel adapter which includes software and firmware adapted for interacting with a specific peripheral device. Each channel adapter also has software and firmware which is device-independent for data transfer with the channel arbitrator. The channel arbitrator includes a memory port for accessing main memory through the CPU, a port for accepting service requests and providing interrupts to the CPU's, direct memory access control logic, arbitration control logic, serial ports associated with the channel adapters, and a parallel port is associated with solid state memory. Direct memory access requests are queued at the channel while higher-priority serial transfer requests are serviced. Direct memory access is provide in 64-word blocks designated by perimeter packets indicating a number of blocks, starting address in main memory, starting address in solid state memory, and an indication of the direction of transfer.

Nibble-Mode Dram Solid State Storage Device

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US Patent:
49512463, Aug 21, 1990
Filed:
Aug 8, 1989
Appl. No.:
7/391229
Inventors:
Eric C. Fromm - Eau Claire WI
Lonnie R. Heidtke - Chippewa Falls WI
Assignee:
Cray Research, Inc. - Minneapolis MN
International Classification:
G06F 1200
US Classification:
364900
Abstract:
A nibble-mode DRAM solid state storage device is organized into a plurality of sections each including a plurality of groups, each including a plurality of ranks of DRAM memory chips. A pipeline data path is provided into and out of each group and nibble-mode access is facilitated by simultaneous pipelining of data into and out of the memory while memory reference operations are accomplished.

Solid State Storage Device

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US Patent:
53216970, Jun 14, 1994
Filed:
May 28, 1992
Appl. No.:
7/890026
Inventors:
Eric C. Fromm - Eau Claire WI
Michael L. Anderson - Eau Claire WI
Lonnie R. Heidtke - Chippewa Falls WI
Assignee:
Cray Research, Inc. - Eagan MN
International Classification:
G06F 1100
US Classification:
371 101
Abstract:
An improved solid state storage device (SSD) with memory organized into a plurality of groups, each group including a plurality of ranks, and each rank having at least two banks sharing a bidirectional data bus. A matrix reorder circuit is used to distribute data across individual memory components in a way that prevents multibit uncorrectable or undetectable errors due to the failure of a single memory component. The matrix reorder circuit is used for both reading and writing data, and operates on a stream of pipelined data of arbitrary length. According to another aspect of this invention, a flaw map and additional hot spare memory are used to electrically replace failing memory components in the According to another aspect of this invention, memory in a bank is accessed during one half of a reference cycle and refreshed during the second half of the reference cycle, each bank being 180 degrees out of phase with the other so that a read or write is performed on one bank while a memory refresh is performed on the other bank.
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Lonnie R Heidtke from Chippewa Falls, WI, age ~75 Get Report