Resumes
Resumes
Leslie Valiant Phones & Addresses
-
50 Tyler Rd, Belmont, MA 02478 (617) 489-4322 (617) 489-7750
-
Cambridge, MA
-
50 Tyler Rd, Belmont, MA 02478
Work
Position:
Executive, Administrative, and Managerial Occupations
Education
Degree:
Associate degree or higher
Publications
Wikipedia
Leslie Valiant
View pageLeslie Gabriel Valiant (born 28 March 1949) is a British computer scientist and computational theorist. He was educated at King's College, Cambridge, ...
Isbn (Books And Publications)
Circuits of the Mind
View page
Author
Leslie G. Valiant
ISBN #
0195126688
Wikipedia References
Leslie Valiant
About:
Born:
28 March 1949
Known for:Valiant–Vazirani theorem
Work:
Company:
Harvard University faculty
Position:Model
Education:
Academic degree:
Member of the United States National Academy of Sciences • Academics of the University of Edinburgh • Professor • Doctor of Philosophy
Studied at:Imperial College London • University of Warwick
Area of science:Computational neuroscience
Skills & Activities:
Ascribed status:
Fellow of the Royal Society • Fellow of the American Association for the Advancement of Science
Skill:Computer science • Algorithms
Us Patents
Multiprogrammed Multiprocessor System With Lobally Controlled Communication And Signature Controlled Scheduling
View pageUS Patent:
6763519, Jul 13, 2004
Filed:
May 5, 1999
Appl. No.:
09/305570
Inventors:
William F. McColl - North Oxford, GB
Jonathan M. D. Hill - Oxford, GB
Leslie G. Valiant - Belmont MA
Stephen R. Donaldson - Oxford, GB
Jonathan M. D. Hill - Oxford, GB
Leslie G. Valiant - Belmont MA
Stephen R. Donaldson - Oxford, GB
Assignee:
Sychron Inc. - San Mateo CA
International Classification:
G06F 946
US Classification:
718100, 718102, 718104, 718107, 709202, 709226, 712 1, 712 28
Abstract:
A multiprogrammed multiprocessor system comprises a plurality of processors and some communications resources such as networks through which the processors communicate with each other. A plurality of tasks may be executed on the system, and the allocation of the communications resources among the tasks is globally controlled. The allocation of resources among the tasks running on the system can be dependent on the signature of the tasks, where one component of a task signature is a measure of the communication resources needed by the task. The scheduling of a task running on the system may also be dependent on the signature of the task. The allocation of communications resources can be globally controlled using a variety of techniques including: packet injection into the communications resources using periodic strobing or using global flow control; using global implicit acknowledgments; by destination scheduling; by pacing; or by prioritized communication scheduling. Error recovery overheads can be amortized over a plurality of jobs running at one node. A user interface allows a plurality of service level options to be specified by a user, where the system can guarantee that the service levels can be achieved.
Bulk-Synchronous Parallel Computer
View pageUS Patent:
50832654, Jan 21, 1992
Filed:
Apr 17, 1990
Appl. No.:
7/510090
Inventors:
Leslie G. Valiant - Belmont MA
Assignee:
President and Fellows of Harvard College - Cambridge MA
International Classification:
G06F 1516
US Classification:
395800
Abstract:
In accordance with the present invention, system architecture and programming are in accordance with a bulk-synchronous parallel processing model. Data is distributed to memory elements through a hashing function performed in individual hardware modules associated with computational elements. The router operates independently of the computational and memory elements and masks any substantial latency it may have by pipelining. A synchronizer provides for bulk synchronization in supersteps of multiple computational steps. The router bandwidth is balanced with that of the computational elements and the program may be compiled to a number of virtual processors significantly greater than the number of actual processors in the system.
System For Combining A Plurality Of Requests Referencing A Common Target Address Into A Single Combined Request Having A Single Reference To The Target Address
View pageUS Patent:
56088701, Mar 4, 1997
Filed:
Jun 2, 1995
Appl. No.:
8/459367
Inventors:
Leslie G. Valiant - Belmont MA
Assignee:
The President and Fellows of Harvard College - Cambridge MA
International Classification:
G06F 1516
G06F 1320
G06F 1320
US Classification:
3952001
Abstract:
Requests are routed between components in a parallel computing system using multiple-phase combining. In the first phase, the original requests are decomposed into groups of requests that share the same destination address. The requests in each group are combined at an intermediate component into a single request per group. In subsequent phases, the combined requests are themselves grouped and combined in intermediate components. In the final phase, the combined requests are processed by the component containing the destination address. The addresses of the intermediate components are determined in part by hashing on the destination address and in part by a distributing function. The hashed portion of the intermediate component address tends to converge the combined requests toward the destination component during each phase. The distributing portion of the intermediate component address tends to distribute the workload evenly among the components.