Inventors:
Robert S. K. Chau - Beaverton OR
William L. Hargrove - Sherwood OR
Leopoldo D. Yau - Portland OR
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
H01L 2131
US Classification:
438773, 438774, 438762, 438297, 438287, 438452, 148DIG 118, 257E21193, 257E21285
Abstract:
A novel process for forming a robust, sub-100 oxide is disclosed. Native oxide growth is tightly controlled by flowing pure nitrogen during wafer push and nitrogen with a small amount of oxygen during temperature ramp and stabilization. First, a dry oxidation is performed in oxygen and 13% trichloroethane. Next, a wet oxidation in pyrogenic steam is performed to produce a total oxide thickness of approximately 80. The oxide layer formed is ideally suited for use as a high integrity gate oxide below 100. The invention is particularly useful in devices with advanced, recessed field isolation where sharp silicon edges are difficult to oxidize. For an oxide layer of more than 100 , a composite oxide stack is used which comprises 40-90 of pad oxide formed using the above novel process, and 60-200 of deposited oxide.