Leopoldo D Yau

RE38674, Dec 21, 2004

Sep 14, 1995

08/528188

Robert S. K. Chau - Beaverton OR
William L. Hargrove - Sherwood OR
Leopoldo D. Yau - Portland OR

Intel Corporation - Santa Clara CA

H01L 2131

438773, 438774, 438762, 438297, 438287, 438452, 148DIG 118, 257E21193, 257E21285

A novel process for forming a robust, sub-100 oxide is disclosed. Native oxide growth is tightly controlled by flowing pure nitrogen during wafer push and nitrogen with a small amount of oxygen during temperature ramp and stabilization. First, a dry oxidation is performed in oxygen and 13% trichloroethane. Next, a wet oxidation in pyrogenic steam is performed to produce a total oxide thickness of approximately 80. The oxide layer formed is ideally suited for use as a high integrity gate oxide below 100. The invention is particularly useful in devices with advanced, recessed field isolation where sharp silicon edges are difficult to oxidize. For an oxide layer of more than 100 , a composite oxide stack is used which comprises 40-90 of pad oxide formed using the above novel process, and 60-200 of deposited oxide.

54880033, Jan 30, 1996

Mar 31, 1993

8/040673

Stephen Chambers - Portland OR
Brian J. Brown - Portland OR
Robert Chau - Beaverton OR
Leopoldo D. Yau - Portland OR

Intel Corporation - Santa Clara CA

H01L 21265

437 31

A new method of isolating a polysilicon emitter from the base region of a bipolar transistor, trenching the polysilicon emitter into the semiconductor substrate, and maintaining a consistent base width of a bipolar transistor independent of variations in emitter mask thicknesses is disclosed. The polysilicon emitter isolation provides for better electrical breakdown characteristics between the emitter and the base by protecting the dielectric layer between the polysilicon emitter and base regions from defects and contamination associated with the BiCMOS manufacturing environment. The polysilicon emitter is trenched into the semiconductor substrate in order to reduce transistor operation problems associated with hot electron injection. Consistent base widths improve transistor performance uniformity thereby improving manufacturability and reliability.

51048191, Apr 14, 1992

Aug 7, 1989

7/390158

Philip E. Freiberger - Santa Clara CA
Leopoldo D. Yau - Portland OR
Cheng-Sheng Pan - Sunnyvale CA
George E. Sery - San Franciso CA

Intel Corporation - Santa Clara CA

H01L 21265
H01L 2176

437 43

A method and a device formed by the method of forming a composite dielectric structure between the floating polysilicon electrode and the control electrode of an EPROM-type device is disclosed. The dielectic is characterized by a thin (0-80 angstroms) thermally-grown or CVD bottom oxide layer covered by a relatively thin (

55540643, Sep 10, 1996

Aug 6, 1993

8/103412

Joseph R. Breivogel - Aloha OR
Samuel F. Louke - Beaverton OR
Michael R. Oliver - Tigard OR
Leopoldo D. Yau - Portland OR
Christopher E. Barns - Portland OR

Intel Corporation - Santa Clara CA

B24B 2900
B24B 722

451 41

A method and apparatus for polishing a thin film formed on a semiconductor substrate. A table covered with a polishing pad is orbited about an axis. Slurry is fed through a plurality of spaced-apart holes formed through the polishing pad to uniformly distribute slurry across the pad surface during polishing. A substrate is pressed face down against the orbiting pad's surface and rotated to facilitate, along with the slurry, the polishing of the thin film formed on the substrate.

49170449, Apr 17, 1990

Jun 2, 1989

7/320526

Leopoldo D. Yau - Portland OR
Galen H. Kawamoto - Beaverton OR

Intel Corporation - Santa Clara CA

C23C 1650

118723

An electrical contact apparatus for use in a plama or glow discharge chamber, particularly a chamber for depositing silicon oxynitride. A feedthrough member provides an electrical path between the interior and exterior of the chamber. An electrical contact member having an outwardly domed surface engages the feedthrough member. A non-conductive collar is disposed about the domed surface for limiting the flow of gas around the domed surface.

60959045, Aug 1, 2000

Feb 1, 1996

8/595182

Joseph R. Breivogel - Aloha OR
Samuel F. Louke - Beaverton OR
Michael R. Oliver - Tigard OR
Leopoldo D. Yau - Portland OR
Christopher E. Barns - Portland OR

Intel Corporation - Santa Clara CA

B24B 722

451 41

A method and apparatus for polishing a thin film formed on a semiconductor substrate. A table covered with a polishing pad is orbited about an axis. Slurry is fed through a plurality of spaced-apart holes formed through the polishing pad to uniformly distribute slurry across the pad surface during polishing. A substrate is pressed face down against the orbiting pad's surface and rotated to facilitate, along with the slurry, the polishing of the thin film formed on the substrate.

46209867, Nov 4, 1986

Oct 15, 1985

6/787537

Leopoldo D. Yau - Durham OR
Robert A. Gasser - Cornelius OR
Kenneth R. Week - Sherwood OR
Jick M. Yu - Beaverton OR
David D. Chin - Aloha OR

Intel Corporation - Santa Clara CA

B05D 512
G03C 726

427 93

A process for the reduction of defect formation in conductive layers of semiconductor bodies during patterning, alloying and passivation. A film of low temperature spin-on-glass containing dye is formed on the conductive layer prior to patterning and any high temperature process greater than 200 degrees C. Hermetic passivation is achieved by depositing on the conductive layer a composite film consisting of a lower, tensile layer and an upper, compressive layer with the net force of the passivation film being tensile.

61394041, Oct 31, 2000

Jan 20, 1998

9/009469

Leopoldo D. Yau - Portland OR

Intel Corporation - Santa Clara CA

B24B 100

451 56

A semiconductor wafer polishing pad conditioner which includes a support structure and a roller which is rotatably mounted to the support structure. The roller has a working surface which is formed with a plurality of blades.