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Lee Gallaher Phones & Addresses

  • Burr Ridge, IL
  • 32882 Haley Rd, Dowagiac, MI 49047
  • Chicago, IL

Resumes

Resumes

Lee Gallaher Photo 1

Lee Gallaher

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Lee Gallaher Photo 2

Lee Gallaher

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Lee Gallaher Photo 3

Lee Gallaher

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Lee Gallaher Photo 4

Broker/ Owner Gallaher Real Estate

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Position:
Broker/ Owner at Gallaher Real Estate
Location:
Mukilteo, Washington
Industry:
Real Estate
Work:
Gallaher Real Estate - Mukilteo WA since Jun 1992
Broker/ Owner

United States Navy - Pear Harbour Hawaii Dec 1978 - Dec 1984
Deep Sea Diver
Skills:
VA
Residential
Real Estate
Foreclosures
Buyer Representation
Single Family Homes
Real Estate Transactions
First Time Buyers
First Time Home Buyers
Purchase
Home
Luxury
HUD
Realty
Distressed Property
Selling
SFR
REO
Brokerage
Resale
Referrals
Contract Negotiation
Investment Properties
Residential Homes
Real Property
Sellers
Property Management
Resellers
Investments
Property
Short Sales
Negotiation
Relocation
Condos
Real Estate Development
Listings
ABR
Investors
Townhomes
New Home Sales
New Homes
Rentals
FHA
Move Up Buyers
Vacation Homes
Waterfront
Income Properties
1031 Exchanges
Buyers
Home Staging
Interests:
Business, investing, painting fine art, NBA, exercise, weight training, reading, philosophy.
Honor & Awards:
Decca College level Washington State Champion 1985-sales. Remax 100% Club 1988. GRE 200% club 1992.

Business Records

Name / Title
Company / Classification
Phones & Addresses
Lee D. Gallaher
President
Decision Data Ltd
Commercial Nonphysical Research Data Processing/Preparation
7962 S Madison St, Willowbrook, IL 60527
(630) 734-8244
Lee D. Gallaher
Principal
Decision Data
Whol Computers/Peripherals
740 94 St, Willowbrook, IL 60527

Publications

Us Patents

Cache Arrangement For Direct Memory Access Block Transfer

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US Patent:
45049025, Mar 12, 1985
Filed:
Mar 25, 1982
Appl. No.:
6/361499
Inventors:
Lee E. Gallaher - Glen Ellyn IL
Wing N. Toy - Glen Ellyn IL
Benjamin Zee - Glen Ellyn IL
Assignee:
AT&T Bell Laboratories - Murray Hill NJ
International Classification:
G06F 900
G06F 1300
G06F 938
US Classification:
364200
Abstract:
A cache memory system reduces cache interference during direct memory access block write operations to main memory. A control memory within cache contains in a single location validity bits for each word in a memory block. In response to the first word transferred at the beginning of a direct memory access block write operation to main memory, all validity bits for the block are reset in a single cache cycle. Cache is thereafter free to be read by the central processor during the time that the remaining words of the block are written without the need for additional cache invalidation memory cycles.
Lee D Gallaher from Burr Ridge, IL, age ~83 Get Report