Resumes
Resumes
Component Design Engineer At Intel Corporation
View pagePosition:
component design engineer at Intel Corporation
Location:
Santa Clara, California
Industry:
Semiconductors
Work:
Intel Corporation - Santa Clara since Jul 2011
component design engineer
Intel Corporation Jul 2010 - Jul 2011
Test R&D Engineer
Reconfigurable Computing Lab Jan 2008 - May 2010
Graduate Research Assistant
University of Arizona, Physics Department Sep 2009 - Dec 2009
Graduate Teaching Assistant
University of Arizona Aug 2007 - Dec 2008
Graduate Teaching Assistant, ECE department
component design engineer
Intel Corporation Jul 2010 - Jul 2011
Test R&D Engineer
Reconfigurable Computing Lab Jan 2008 - May 2010
Graduate Research Assistant
University of Arizona, Physics Department Sep 2009 - Dec 2009
Graduate Teaching Assistant
University of Arizona Aug 2007 - Dec 2008
Graduate Teaching Assistant, ECE department
Education:
University of Arizona 2007 - 2010
Master of Sciences, Electrical And Computer Engineering Anna University 2002 - 2006
Bachelor of Engineering, Electrical and Electronics Engineering
Master of Sciences, Electrical And Computer Engineering Anna University 2002 - 2006
Bachelor of Engineering, Electrical and Electronics Engineering
Skills:
Verilog
C
Embedded Systems
C++
FPGA
Cadence Virtuoso
VLSI
Computer Architecture
Shell Scripting
Debugging
C
Embedded Systems
C++
FPGA
Cadence Virtuoso
VLSI
Computer Architecture
Shell Scripting
Debugging
Honor & Awards:
PUBLICATIONS
• A. Pandit, L. Easwaran A. Akoglu, “Concurrent timing based and routability driven depopulation technique for FPGA packing’, International Conference on Field-Programmable Technology 2008 (ICFPT'08).
PERSONAL ACCOMPLISHMENTS
• Won outstanding student award for the academic year 1999- 2000, awarded by Lions Club of Central Madras.
• Awarded the Graduate Tuition Scholarship by ECE Department, University of Arizona.
Languages:
python
Lakshmi Easwaran
View pageLocation:
San Francisco, CA
Industry:
Semiconductors
Work:
Intel Corporation Feb 2018 - Jan 2018
Design Verification Engineer
Reconfigurable Computing Lab Jan 2008 - May 2010
Graduate Research Assistant
Design Verification Engineer
Reconfigurable Computing Lab Jan 2008 - May 2010
Graduate Research Assistant
Education:
University of Arizona 2007 - 2010
Master of Science, Masters, Computer Engineering Anna University 2002 - 2006
Bachelor of Engineering, Bachelors, Electronics Engineering
Master of Science, Masters, Computer Engineering Anna University 2002 - 2006
Bachelor of Engineering, Bachelors, Electronics Engineering
Skills:
Verilog
C
C++
Embedded Systems
Debugging
Linux
Fpga
Simulations
Emulation
Python
Cadence Virtuoso
Vlsi
Computer Architecture
Shell Scripting
Unix
Testing
Programming
C
C++
Embedded Systems
Debugging
Linux
Fpga
Simulations
Emulation
Python
Cadence Virtuoso
Vlsi
Computer Architecture
Shell Scripting
Unix
Testing
Programming
Interests:
Children
Education
Environment
Science and Technology
Disaster and Humanitarian Relief
Arts and Culture
Health
Education
Environment
Science and Technology
Disaster and Humanitarian Relief
Arts and Culture
Health