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Kunal Vaed

from New York, NY
Age ~48
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Connected to:
Donald B Vaello, 78Cassandra Vaesa, 43Daniel W Vaessen, 62Luke A Vaessen, 50Carol L Vaeth, 61David R Vaeth, 59Dean G Vaeth, 77Frederick C Vaeth, 60Laura A Vaeth, 31Hossein Vaez, 52

Kunal Vaed Phones & Addresses

  • 101 E 16Th St #4J, New York, NY 10003
  • 203 76Th St, New York, NY 10021 (646) 684-4451
  • 203 E 76Th St #2G, New York, NY 10021 (646) 684-4451
  • 39 Plaza St W APT 6C, Brooklyn, NY 11217
  • West New York, NJ
  • Wappingers Falls, NY
  • Poughkeepsie, NY
  • Beacon, NY
  • Columbus, OH

Work

Company: Jpmorgan chase & co. Jan 2017 Position: Managing director, head of digital - self directed investing

Education

Degree: Master of Business Administration, Masters School / High School: Nyu Stern School of Business 2004 to 2007 Specialities: Corporate Finance

Skills

Strategy • Management Consulting • Business Strategy • Business Transformation • Business Development • Cross Functional Team Leadership • Product Management • Leadership • Semiconductors • Strategic Partnerships • Mergers and Acquisitions • Financial Modeling • Go To Market Strategy • Analysis • Valuation • Start Ups • Management • Retail Banking • Customer Experience • R&D • Wealth Management • Payments • Big Data • Digitization • Client Experience

Languages

Hindi

Interests

Shasta Ventures • Joi Ito • Caterina Fake • Reid Hoffman • Venturebeat • John Doerr • Gigaom • First Round Capital • Paul Graham • Bing Gordon • Marc Andreessen • Pierre Omidyar • Rre Ventures • Google Ventures • Sean Parker • Accel Partners • Greylock Partners • Wired (Magazine)

Industries

Financial Services

Resumes

Resumes

Kunal Vaed Photo 1

Managing Director, Head Of Digital - Self Directed Investing

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Location:
New York, NY
Industry:
Financial Services
Work:
Jpmorgan Chase & Co.
Managing Director, Head of Digital - Self Directed Investing
E*Trade Oct 2013 - Sep 2016
Senior Vice President, Head of Digital
Strategy&, Part of the Pwc Network Oct 2007 - Oct 2013
Principal
Booz Digital Dec 2012 - Oct 2013
Principal
Ibm Jun 2006 - Oct 2007
Business Strategist
Education:
Nyu Stern School of Business 2004 - 2007
Master of Business Administration, Masters, Corporate Finance The Ohio State University 1999 - 2001
Master of Science, Masters, Materials Science, Engineering The Ohio State University 2001
College of Engineering Pune 1995 - 1999
Bachelor of Engineering, Bachelors Department of Technology, Savitribai Phule Pune University 1999
Master of Science, Masters New York University
Skills:
Strategy
Management Consulting
Business Strategy
Business Transformation
Business Development
Cross Functional Team Leadership
Product Management
Leadership
Semiconductors
Strategic Partnerships
Mergers and Acquisitions
Financial Modeling
Go To Market Strategy
Analysis
Valuation
Start Ups
Management
Retail Banking
Customer Experience
R&D
Wealth Management
Payments
Big Data
Digitization
Client Experience
Interests:
Shasta Ventures
Joi Ito
Caterina Fake
Reid Hoffman
Venturebeat
John Doerr
Gigaom
First Round Capital
Paul Graham
Bing Gordon
Marc Andreessen
Pierre Omidyar
Rre Ventures
Google Ventures
Sean Parker
Accel Partners
Greylock Partners
Wired (Magazine)
Languages:
Hindi

Publications

Us Patents

Damascene Integration Scheme For Developing Metal-Insulator-Metal Capacitors

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US Patent:
6992344, Jan 31, 2006
Filed:
Dec 13, 2002
Appl. No.:
10/319724
Inventors:
Douglas D. Coolbaugh - Essex Junction VT, US
John M. Cotte - New Fairfield CT, US
Ebenezer E. Eshun - Essex Junction VT, US
Kenneth J. Stein - Sandy Hook CT, US
Kunal Vaed - Poughkeepsie NY, US
Richard P. Volant - New Fairfield CT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 27/108
US Classification:
257301, 257303, 257304, 257306, 257310, 257324, 257397, 257532
Abstract:
The invention is directed to unique high-surface area BEOL capacitor structures with high-k dielectric layers and methods for fabricating the same. These high-surface area BEOL capacitor structures may be used in analog and mixed signal applications. The capacitor is formed within a trench with pedestals within the trench to provide additional surface area. The top and bottom electrodes are created using damascene integration scheme. The dielectric layer is created as a multilayer dielectric film comprising for instance AlO, AlO/TaO, AlO/TaO/AlOand the like. The dielectric layer may be deposited by methods like atomic layer deposition or chemical vapor deposition. The dielectric layer used in the capacitor may also be produced by anodic oxidation of a metallic precursor to yield a high dielectric constant oxide layer.

Method Of Forming Suspended Transmission Line Structures In Back End Of Line Processing

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US Patent:
7005371, Feb 28, 2006
Filed:
Apr 29, 2004
Appl. No.:
10/709357
Inventors:
Anil K. Chinthakindi - Poughkeepsie NY, US
Robert A. Groves - Highland NY, US
Youri V. Tretiakov - South Burlington VT, US
Kunal Vaed - Poughkeepsie NY, US
Richard P. Volant - New Fairfield CT, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/4763
US Classification:
438618, 438619, 438622
Abstract:
A method for forming a transmission line structure for a semiconductor device includes forming an interlevel dielectric layer over a first metallization level, removing a portion of the interlevel dielectric layer and forming a sacrificial material within one or more voids created by the removal of the portion of the interlevel dielectric layer. A signal transmission line is formed in a second metallization level formed over the interlevel dielectric layer, the signal transmission line being disposed over the sacrificial material. A portion of dielectric material included within the second metallization level is removed so as to expose the sacrificial material, wherein a portion of the sacrificial material is exposed through a plurality of access holes formed through the signal transmission line. The sacrificial material is removed so as to create an air gap beneath the signal transmission line.

Hi-K Dielectric Layer Deposition Methods

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US Patent:
7354872, Apr 8, 2008
Filed:
May 26, 2005
Appl. No.:
10/908789
Inventors:
Douglas D. Coolbaugh - Essex Junction VT, US
Ebenezer E. Eshun - Essex Junction VT, US
Kenneth J. Stein - Sandy Hook CT, US
Kunal Vaed - Poughkeepsie NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/31
H01L 21/469
US Classification:
438778, 257E21478, 257E21494, 438785, 438789
Abstract:
Methods of forming a high dielectric constant dielectric layer are disclosed including providing a process chamber including a holder for supporting a substrate, introducing a first gas comprising a high dielectric constant (Hi-K) dielectric precursor and an oxygen (O) oxidant into the process chamber to form a first portion of the high dielectric constant dielectric layer on the substrate, and switching from a flow of the first gas to a flow of a second gas comprising the Hi-K dielectric precursor and an ozone (O) oxidant to form a second portion of the high dielectric constant dielectric layer on the first portion. In an alternative embodiment, another portion can be formed on the second portion using the oxygen oxidant. The invention increases throughput by at least 20% without reliability or leakage degradation and without the need for additional equipment.

Methods Of Fabricating Passive Element Without Planarizing And Related Semiconductor Device

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US Patent:
7394145, Jul 1, 2008
Filed:
Oct 30, 2007
Appl. No.:
11/928798
Inventors:
Anil K Chinthakindi - Wappingers Falls NY, US
Timothy J. Dalton - Ridgefield CT, US
Ebenezer E. Eshun - Newburgh NY, US
Jeffrey P. Gambino - Westford VT, US
Anthony K. Stamper - Williston VT, US
Kunal Vaed - Poughkeepsie NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 29/00
H01L 21/20
US Classification:
257528, 257532, 257536, 257E27047, 257E27048, 438381, 438384, 438393
Abstract:
Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

Post Last Wiring Level Inductor Using Patterned Plate Process

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US Patent:
7410894, Aug 12, 2008
Filed:
Jul 27, 2005
Appl. No.:
11/161217
Inventors:
Anil K. Chinthakindi - Poughkeepsie NY, US
Douglas D. Coolbaugh - Essex Junction VT, US
John E. Florkey - Pleasant Valley NY, US
Jeffrey P. Gambino - Westford VT, US
Zhong-Xiang He - Essex Junction VT, US
Anthony K. Stamper - Williston VT, US
Kunal Vaed - Poughkeepsie NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/44
H01L 21/20
H01L 29/00
US Classification:
438612, 438381, 438622, 257531
Abstract:
A method of forming a semiconductor structure, and the semiconductor structure so formed, wherein a transmission line, such as an inductor, is formed on a planar level above the surface of a last metal wiring level.

Methods Of Fabricating Passive Element Without Planarizing

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US Patent:
7427550, Sep 23, 2008
Filed:
Jun 29, 2006
Appl. No.:
11/427457
Inventors:
Anil K. Chinthakindi - Wappingers Falls NY, US
Timothy J. Dalton - Ridgefield CT, US
Ebenezer E. Eshun - Newburgh NY, US
Jeffrey P. Gambino - Westford VT, US
Anthony K. Stamper - Williston VT, US
Kunal Vaed - Poughkeepsie NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/20
US Classification:
438381, 438384, 438393
Abstract:
Methods of fabricating a passive element and a semiconductor device including the passive element are disclosed including the use of a dummy passive element. A dummy passive element is a passive element or wire which is added to the chip layout to aid in planarization but is not used in the active circuit. One embodiment of the method includes forming the passive element and a dummy passive element adjacent to the passive element; forming a dielectric layer over the passive element and the dummy passive element, wherein the dielectric layer is substantially planar between the passive element and the dummy passive element; and forming in the dielectric layer an interconnect to the passive element through the dielectric layer and a dummy interconnect portion overlapping at least a portion of the dummy passive element. The methods eliminate the need for planarizing.

Method And Structure For Integrating Mim Capacitors Within Dual Damascene Processing Techniques

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US Patent:
7439151, Oct 21, 2008
Filed:
Sep 13, 2006
Appl. No.:
11/531298
Inventors:
Douglas D. Coolbaugh - Highland NY, US
Timothy J. Dalton - Ridgefield CT, US
Ebenezer Eshun - Newburgh NY, US
Vincent J. McGahay - Poughkeepsie NY, US
Anthony K. Stamper - Williston VT, US
Kunal Vaed - Poughkeepsie NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 21/20
US Classification:
438387, 438389, 257E21016
Abstract:
A method for integrating the formation of metal-insulator-metal (MIM) capacitors within dual damascene processing includes forming a lower interlevel dielectric (ILD) layer having a lower capacitor electrode and one or more lower metal lines therein, the ILD layer having a first dielectric capping layer formed thereon. An upper ILD layer is formed over the lower ILD layer, and a via and upper line structure are defined within the upper ILD layer. The via and upper line structure are filled with a planarizing layer, followed by forming and patterning a resist layer over the planarizing layer. An upper capacitor electrode structure is defined in the upper ILD layer corresponding to a removed portion of the resist. The via, upper line structure and upper capacitor electrode structure are filled with conductive material, wherein a MIM capacitor is defined by the lower capacitor electrode, first dielectric capping layer and upper capacitor electrode structure.

Mos Varactor With Segmented Gate Doping

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US Patent:
7545007, Jun 9, 2009
Filed:
Aug 8, 2005
Appl. No.:
11/161533
Inventors:
Heidi L. Greer - Essex Junction VT, US
Robert M. Rassel - Colchester VT, US
Kunal Vaed - Poughkeepsie NY, US
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 29/76
US Classification:
257386, 257E27049, 257E29344
Abstract:
A MOS varactor is formed having a gate electrode comprising at least two abutting oppositely doped regions shorted together, in which the two regions are implanted simultaneously with source/drain implants for first and second types of transistor; at least one contact to a lower electrode is also formed simultaneously with the source/drain implants for the first type of transistor; the varactor insulator is formed simultaneously with the gate insulator for one type of transistor; and the lower electrode is formed simultaneously with a well for the first type of transistor, so that no additional mask is required.
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Kunal Vaed from New York, NY, age ~48 Get Report