Resumes
Resumes
Kristin Richling Phones & Addresses
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Severance, CO
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4231 Goldenridge Way, Fort Collins, CO 80526 (970) 229-9163
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Windsor, CO
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Monument, CO
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PO Box 85, Severance, CO 80546
Work
Position:
Professional/Technical
Education
Degree:
Graduate or professional degree
Emails
Publications
Us Patents
System And Method For Simplifying Clock Construction And Analysis
View pageUS Patent:
20030149950, Aug 7, 2003
Filed:
Feb 5, 2002
Appl. No.:
10/068646
Inventors:
Kristin Richling - Fort Collins CO, US
Gayvin Stong - Fort Collins CO, US
Edgardo Lopez - Fort Collins CO, US
Guy Humphrey - Fort Collins CO, US
Richard Krzyzkowski - Ft. Collins CO, US
Laurent Pinot - Fort Collins CO, US
Gayvin Stong - Fort Collins CO, US
Edgardo Lopez - Fort Collins CO, US
Guy Humphrey - Fort Collins CO, US
Richard Krzyzkowski - Ft. Collins CO, US
Laurent Pinot - Fort Collins CO, US
International Classification:
G06F009/45
G06F017/50
G06F017/50
US Classification:
716/006000
Abstract:
A system for simplifying clock construction and distribution within an integrated circuit, and for simplifying analysis within the integrated circuit. The system utilizes a memory, software stored within said memory defining functions to be performed by the system, and a processor. The processor is configured by the software to: read a defined location for a clock generator within the integrated circuit, wherein the clock generator generates a clock signal; read a defined number of interconnect routes to be created within the integrated circuit, wherein a subset of the number of interconnect routes corresponds to a number of logical blocks that will later be provided within the integrated circuit, and wherein each of the interconnect routes within the subset comprises an open end for one of the logical blocks to be placed; test electrical characteristics and functionality of the integrated circuit to ensure that a time for the clock signal to traverse each of the interconnect routes within the subset is equal, and change properties within the integrated circuit if the clock signal traversal time is not equal; and add the logical blocks to each of the interconnect routes within the subset, wherein each of the logical blocks is connected to the open end of one of the interconnect routes within the subset.