Klaus H Koop

55939074, Jan 14, 1997

Mar 8, 1995

8/400609

Mohammed Anjum - Austin TX
Klaus H. Koop - Elgin TX
Maung H. Kyaw - Austin TX

Advanced Micro Devices - Sunnyvale CA

H01L 21265

437 35

A semiconductor structure with large tile angle boron implant is provided for reducing threshold shifts or rolloff at the channel edges. By minimizing threshold shifts, short channel effects and subthreshold currents at or near the substrate surface are lessened. The semiconductor structure is prepared by implanting boron at a non-perpendicular into the juncture between the channel and the source/drain as well as the juncture between the field areas and the source/drain. Placement of boron into these critical regions replenishes segregating and redistributing threshold adjust implant species and channel stop implant species resulting from process temperature cycles. Using lighter boron ions allow for a lesser annealing temperature and thereby avoids the disadvantages of enhanced redistribution and diffusion caused by high temperature anneal.

53607490, Nov 1, 1994

Dec 10, 1993

8/166305

Mohammed Anjum - Austin TX
Klaus H. Koop - Elgin TX
Maung H. Kyaw - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 21265

437 24

A semiconductor structure with germanium implant is provided for reducing V. sub. T shifts at the channel edges thereby minimizing short channel effects and subthreshold currents at or near the substrate surface. The semiconductor structure is adapted to receive non-perpendicular implant of germanium in the juncture between the channel and the source/drain regions as well as in the juncture between field oxide channel stop implant and source/drain regions. By carefully and controllably placing the germanium at select channel and field regions, segregation and redistribution of threshold adjust implant and channel stop implant dopant materials is substantially minimized. Reducing the redistribution of such materials provides a reduction in the short channel effects and, particularly, a reduction in substrate surface current or DIBL-induced current.

54299721, Jul 4, 1995

May 9, 1994

8/239453

Mohammed Anjum - Austin TX
Klaus H. Koop - Elgin TX
Maung H. Kyaw - Austin TX

Advanced Micro Devices, Inc. - Sunnyvale CA

H01L 21265

437 47

An enhanced capacitor configuration is provided in which the conductive and insulative layers are formed by implantation rather than deposition. The conductive regions are implanted at dissimilar depths and the insulative region is implanted between the conductive regions to form the conductive plates and intermediate dielectric material. By implanting rather than depositing, the dielectric material remains free of pinholes and can be configured thinner than conventional dielectrics, with a higher dielectric constant (k) due to the absence of an oxide. Moreover, cross-diffusions which occur during the anneal step allow texturization of the dielectric/conductive juncture. Texturization corresponds to an increase in surface area of the capacitor and, similar to increase in dielectric constant and decrease in dielectric thickness, increases the capacitive value of the ensuing capacitor.