Search

Kevin Lowderman Phones & Addresses

  • 1810 Windsong Trl, Richardson, TX 75081 (972) 690-6719
  • Dallas, TX
  • 1810 Windsong Trl, Richardson, TX 75081 (214) 357-3131

Work

Company: Independent contractor 2002 to 2010 Position: Embedded hardware designer

Education

Degree: MSEE School / High School: Virginia Polytechnic Institute and State University 1981 to 1982 Specialities: Computers, Electronics

Languages

English

Industries

Consumer Electronics

Resumes

Resumes

Kevin Lowderman Photo 1

Kevin Lowderman

View page
Location:
1810 Windsong Trl, Richardson, TX 75081
Industry:
Consumer Electronics
Work:
Independent Contractor 2002 - 2010
Embedded Hardware Designer

Tekgenix, Inc. 1999 - 2002
Member Technical Staff

DNA, Inc. 1997 - 1999
Hardware Design Engineer

Mizar, Inc. 1995 - 1997
Hardware Design Engineer

Convex Computer Corporation 1986 - 1994
Hardware Design Engineer
Education:
Virginia Polytechnic Institute and State University 1981 - 1982
MSEE, Computers, Electronics
Graceland University 1977 - 1981
BSCE,BSCS, Computers, Electronics
Languages:
English

Business Records

Name / Title
Company / Classification
Phones & Addresses
Kevin Lowderman
Principal
Aava Technologies
Business Services at Non-Commercial Site
1810 Windsong Trl, Richardson, TX 75081

Publications

Us Patents

Error Detecting Method And Apparatus For Computer Memory Having Multi-Bit Output Memory Circuits

View page
US Patent:
52914984, Mar 1, 1994
Filed:
Jan 29, 1991
Appl. No.:
7/647408
Inventors:
James A. Jackson - Richardson TX
Marc A. Quattromani - Allen TX
Kevin M. Lowderman - Richardson TX
Assignee:
Convex Computer Corporation - Richardson TX
International Classification:
H03M 1300
US Classification:
371 401
Abstract:
An error correcting code and apparatus are used in conjunction with a main memory in which a data word is stored in a plurality of circuits each of which produces multiple outputs. A minimum number of check bits are stored together with the data word for detecting and correcting single bit errors and detecting the existence of multi-bit errors. A parity bit for the entire data word is also stored. For a 32-bit data word, at least 3 bits of the data word are stored in each of 10 memory circuits. Seven check bits and one parity bit are also stored in the 10 memory circuits wherein no more than one of the check bits or parity bit is stored in any one memory circuit. Upon reading the data word from the memory a set of verify check bits and a verify parity bit are generated and compared to the stored check bits and stored parity bit to produce a check bit syndrome and a parity bit syndrome. The check bit syndrome is decoded to produce an output that is input to an error generator circuit together with a parity syndrome for producing error signals indicating occurrence of a single bit error, a multi-bit error, a triple bit error, or a check bit error.
Kevin M Lowderman from Richardson, TX, age ~65 Get Report