Kevin L Kloker

20080120264, May 22, 2008

Nov 20, 2006

11/561491

Whay Chiou Lee - Cambridge MA, US
Charbel Khawand - Miami FL, US
Kevin L. Kloker - Palatine IL, US
Stephen N. Levine - Itasca IL, US

Motorola, Inc. - Schaumburg IL

G06F 17/00

706 47

A method and apparatus for efficient management of hierarchically administered spectrum resources in a communications network are disclosed. The method may include receiving a request for a policy decision from a policy enforcement point at a current policy decision point level in a hierarchy of policy decision points, determining whether the request can be satisfied at the current policy decision point level, wherein if the request cannot be satisfied at the current policy decision point level, forwarding the request to a policy decision point at a policy decision point level that is higher in the hierarchy, otherwise retrieving policy information from a policy database, determining a policy decision, wherein if the request was received from the policy enforcement point at the current policy decision point hierarchy level, sending the policy decision to the policy enforcement point at the current policy decision point level in the hierarchy, otherwise, sending the policy decision to a policy decision point level lower in the hierarchy.

20080159208, Jul 3, 2008

Dec 28, 2006

11/617018

Kevin L. Kloker - Palatine IL, US
Gregory J. Buchwald - Crystal Lake IL, US
Lawrence M. Ecklund - Wheaton IL, US
Stephen L. Kuffner - Algonquin IL, US
Stephen N. Levine - Itasca IL, US
S. David Silk - Barrington IL, US

MOTOROLA, INC. - Schaumburg IL

H04Q 7/00

370329

A method and apparatus for allocation of shared spectrum in a wireless communication system uses a radio frequency (RF) beacon signal that is transmitted between access points of the wireless communication system. The information content of the RF beacon signal includes an identifier of the access point that generated the signal, identifiers of clients of that access point; and identifiers of the communication channels assigned to those clients. The client identifier may include at least part of an Internet Protocol (IP) address of the client. Additionally the beacon signal may contain client attributes to enable negotiation of the sharing of available communication channels between access points and clients.

47440430, May 10, 1988

Mar 25, 1985

6/715863

Kevin L. Kloker - Arlington Heights IL

Motorola, Inc. - Schaumburg IL

G06F 738
G06F 772

364736

A data processor execution unit is provided for coupling multiple operands to an AU in response to an operand selection portion of an instruction supplied from an instruction register. At least two operands are provided from two pluralities of registers, respectively. Additionally, a predetermined one of the operands contains encoded information for selecting one of a plurality of arithmetic operations which the AU performs. The operand containing the encoded information is coupled to an AU control decoder for use in controlling the operation of the AU. In one form, a single operand selection portion of an instruction selects a plurality of registers containing operands which the AU may utilize. In another form, one of the operands contains encoded information for use in selecting arithmetic formats of the AU.

45396841, Sep 3, 1985

Jan 7, 1983

6/456233

Kevin L. Kloker - Arlington Heights IL

Motorola, Inc. - Schaumburg IL

G06F 1110

371 46

A digital communication system including an encoder and decoder for the transmission of digital information over a transmission medium, the system having automatic frame synchronization and error correction requiring a minimum of tansmission bits and decoding time. The encoder processes a data stream and generates a transmission bit stream of N bits using convolutional encoding, autosynchronization sequence combining, and bit interleaving. The multi-phase sequential decoder decodes the received coded data, corrects transmission errors and automatically achieves frame synchronization from P selected phases of the received data. This is accomplished by selecting the phase of the received data with the best metric, bit de-interleaving, removing the autosynchronization sequence and comparing the received data of the selected phase with the extended code word subsets from the node having the best metric. The decoder then selects a new best metric node and phase in an iterative process until the decoding operation terminates with either valid decoded data upon reaching a terminal node or a code word erasure due to computation or memory overflow. Thus the decoder simultaneously searches for the correct phase and decoded data by iteratively maximizing the code word metric in one decoding operation.

47424796, May 3, 1988

Mar 25, 1985

6/715864

Kevin L. Kloker - Arlington Heights IL
Miles P. Posen - Chicago IL

Motorola, Inc. - Schaumburg IL

G06F 772

364746

A modulo arithmetic unit for providing a sum or difference of two numbers of arbitrary value in a selected one of a plurality of moduli is provided. Each modulus has a lower and an upper boundary and a range of intermediate values. First and second adders are provided for respectively providing first and second outputs which respectively represent outputs compensated for and not compensated for a possible wraparound of the upper or lower boundary. Control circuitry is used to detect whether a wraparound occurred during the calculation depending upon the value of selective interstage carry signals of the first and second adders. The correct output is provided as a selected one of the outputs of the first and second adders in response to the control circuitry.

58450980, Dec 1, 1998

Jun 24, 1996

8/669680

David Galanti - Natania, IL
Eitan Zmora - Jerusalem, IL
Natan Baron - Oranit, IL
Kevin Kloker - Palatine IL

Motorola Inc. - Schaumburg IL

G06F 1340

395307

Subsystems (12-20) are coupled by a bus (44) which includes higher order address lines (62, 64) and lower order address lines (60). One or more subsystems (20) has an address connection (202) for receiving lower order addresses (76') identifying an address space (INT) within this subsystem (20). This connection (202) is coupled to the higher order address lines (62, 64) of the bus (44). An address generator (22) provides subsystem select (CS) addresses and lower order (INT) addresses. A control means (24) coupled between the address generator (22) and the bus (44), uses the subsystem select (CS) addresses to dynamically couple the lower order (INT) addresses from the address generator (22) to the higher order bus lines (62, 64) when the subsystem select (CS) address is for the chosen subsystem (20). This reduces the number of subsystems (12-20) coupled to the lower order bus lines (60) and helps equalize bus (44) loading.

47093242, Nov 24, 1987

Nov 27, 1985

6/802491

Kevin L. Kloker - Arlington Heights IL

Motorola, Inc. - Schaumburg IL

G06F 1506

364200

A data processor control unit which provides instructions for execution by a data processor and minimizes instruction cycles lost as overhead. A pipelined instruction stream is used in which instruction addresses are selectively coupled from a program counter and a prefetch counter to a program memory which provides actual instructions. The instructions are stored in a prefetched register, decoded and then loaded into an instruction register coupled to the data processor. When an interrupt service request is made by a device peripheral to the processor, the prefetch instruction address flow is immediately redirected and a predetermined number of interrupt instruction words are prefetched by an interrupt address generator before completion of execution of normal program instructions has occurred. Therefore, interrupt instructions are fetched and jammed into a pipelined instruction stream regardless of instruction cycle boundaries. Similarly, prefetch instruction address flow is redirected back to normal instruction words before completion of the decoding and execution of interrupt service instructions so that substantially no instruction execution cycles of the data processor are lost as overhead.

52788741, Jan 11, 1994

Sep 2, 1992

7/939745

Clif Liu - San Diego CA
Kevin L. Kloker - Arlington Heights IL
Thomas L. Wernimont - Palatine IL

Motorola, Inc. - Schaumburg IL

H03D 324

375120

A phase lock loop circuit (10) which locks to a frequency within a range of input signal frequencies. A frequency discriminator (12) of phase lock loop circuit (10) determines a maximum pulse width of the input signal by counting a number of pulses of a reference signal in each of a series of pulses of the input signal. A coarse frequency controller (16) compares the maximum pulse width to two threshold values to determine whether the reference signal should be coarsely or finely adjusted. If the reference signal is coarsely adjusted, control circuit (16) provides a coarse frequency control signal to indicate whether a voltage controlled oscillator, VCO, (26) should increase or decrease the reference frequency. If the reference frequency is finely adjusted, a phase discriminator (22) provides a fine frequency control signal to the VCO to either increase or decrease the frequency of the reference signal with greater resolution.