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Ketan Anisha Sodha

from Fremont, CA
Age ~56
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Also known as:
Sodha Ketan
Phone and address:
48937 Nampeyo St, Fremont, CA 94539
(510) 440-8325
Related to:
Shalini D Anadkat, 44Vierenda SodhaBharati V Sodha, 81Anil G Shah, 84Mital S Dadlani, 51Chi D Phan, 51Virendra V SodhaAnisha A Shah, 55Mradula A Shah, 84
Connected to:
Piyush Sodha, 66Sudhir V Sodha, 78Amit Sodhi, 39Hardeep K Sodhi, 52Harneet Sodhi, 44Harvinder Sodhi, 83Jagjit Sodhi, 101Manmohan S Sodhi, 86Misha Sodhi, 38Ravjot S Sodhi, 40

Ketan Sodha Phones & Addresses

  • 48937 Nampeyo St, Fremont, CA 94539 (510) 440-8325
  • 4175 Redstone Ter, Fremont, CA 94555
  • Surprise, AZ
  • Milpitas, CA
  • Alameda, CA

Work

Company: Xilinx 2006 to 2012 Position: Senior integrated circuit design manager

Education

Degree: Masters School / High School: Santa Clara University Specialities: Electronics Engineering

Skills

Signal Integrity • Verilog • Fpga • Analog Circuit Design • Product Development • Ic • Project Management • Digital Ic Design • Modeling • Risk Management • Managing Workflow

Industries

Semiconductors

Resumes

Resumes

Ketan Sodha Photo 1

Director And Senior Manager, Ip Development

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Location:
San Francisco, CA
Industry:
Semiconductors
Work:
Xilinx 2006 - 2012
Senior Integrated Circuit Design Manager
Lattice Semiconductor 2006 - 2012
Director and Senior Manager, Ip Development
Xilinx 2001 - 2006
Staff Ic Designer
Xilinx 1997 - 2001
Senior Ic Designer
Education:
Santa Clara University
Masters, Electronics Engineering
Skills:
Signal Integrity
Verilog
Fpga
Analog Circuit Design
Product Development
Ic
Project Management
Digital Ic Design
Modeling
Risk Management
Managing Workflow

Publications

Us Patents

Bias Voltage Generator Usable With Circuit For Producing Low-Voltage Differential Signals

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US Patent:
6531892, Mar 11, 2003
Filed:
Jan 14, 2002
Appl. No.:
10/047158
Inventors:
Atul V. Ghia - San Jose CA
Ketan Sodha - Fremont CA
Assignee:
Xilinx Inc. - San Jose CA
International Classification:
H03K 19094
US Classification:
326 50, 326 49, 326 87
Abstract:
Described are systems for producing differential logic signals and circuits for biasing the voltages of the differential logic signals. These systems can be adapted for use with different loads by programming one or more programmable elements. One embodiment includes a series of driver stages, the outputs of which are connected to one another. The driver stages turn on successively to provide increasingly powerful differential amplification. This progressive increase in amplification produces a corresponding progressive decrease in output resistance, which reduces the noise associated with signal reflection. The systems can be incorporated into programmable IOBs to enable PLDs to provide differential output signals.

Double Data Rate Flip-Flop

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US Patent:
6777980, Aug 17, 2004
Filed:
Jan 15, 2003
Appl. No.:
10/342574
Inventors:
Steven P. Young - Boulder CO
Suresh M. Menon - Sunnyvale CA
Ketan Sodha - Fremont CA
Richard A. Carberry - Los Gatos CA
Joseph H. Hassoun - Los Gatos CA
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 19173
US Classification:
326 41, 326 37, 326 46
Abstract:
Method and apparatus for doubling the throughput rate of data transmission on a logic path comprising providing two latches that alternately receive successive bits of the data stream to be transmitted and a multiplexer having data transmission paths that are alternately clocked by two separate clocks, which clocks are substantially 180 degrees out of phase.

Programmable Differential Internal Termination For A Low Voltage Differential Signal Input Or Output Buffer

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US Patent:
6963219, Nov 8, 2005
Filed:
Apr 8, 2003
Appl. No.:
10/409891
Inventors:
Atul V. Ghia - San Jose CA, US
Ketan Sodha - Fremont CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K017/16
US Classification:
326 30, 326 86, 327321
Abstract:
A configurable low voltage differential signal (LVDS) system is located on a chip, such as a programmable logic device. The configurable LVDS system includes a pair of I/O pads, an LVDS transmitter for driving a differential output signal onto the I/O pads, an LVDS receiver for receiving a differential input signal from the I/O pads, and a termination resistor coupled across the pair of I/O pads, wherein the termination resistance can be enabled for use with either the LVDS transmitter or the LVDS receiver. Control circuitry is provided to control the selective enabling and disabling of the LVDS transmitter, the LVDS receiver and the termination resistance. This control circuitry can be configured in response to configuration data values stored on the chip.

Multi-Purpose Source Synchronous Interface Circuitry

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US Patent:
7091890, Aug 15, 2006
Filed:
Aug 17, 2004
Appl. No.:
10/919901
Inventors:
Paul T. Sasaki - Sunnyvale CA, US
Jason R. Bergendahl - Sunnyvale CA, US
Atul Ghia - San Jose CA, US
Hassan Bazargan - San Jose CA, US
Ketan Sodha - Fremont CA, US
Jian Tan - Fremont CA, US
Qi Zhang - Milpitas CA, US
Suresh Menon - Sunnyvale CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03M 9/00
US Classification:
341100, 341 59
Abstract:
A serializer-deserializer instantiated in configurable logic of an integrated circuit is described. The serializer-deserializer includes an input deserializer and an output serializer, which may be commonly coupled via an input/output pad. Each of the serializer and deserializer may be configured for an operating mode selected from a Single Data Rate mode and a Double Data Rate mode. The serializer-deserializer may be used as part of a synchronous interface.

Double Data Rate Flip-Flop

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US Patent:
7317773, Jan 8, 2008
Filed:
Jul 9, 2004
Appl. No.:
10/888203
Inventors:
Steven P. Young - Boulder CO, US
Suresh M. Menon - Sunnyvale CA, US
Ketan Sodha - Fremont CA, US
Richard A. Carberry - Los Gatos CA, US
Joseph H. Hassoun - Los Gatos CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H04L 7/00
US Classification:
375354, 326 41
Abstract:
Method and apparatus for doubling the throughput rate of data transmission on a logic path comprising providing two latches that alternately receive successive bits of the data stream to be transmitted and a multiplexer having data transmission paths that are alternately clocked by two separate clocks, which clocks are substantially 180 degrees out of phase.

Method And Apparatus For A Process, Voltage, And Temperature Variation Tolerant Semiconductor Device

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US Patent:
7728630, Jun 1, 2010
Filed:
Jan 29, 2009
Appl. No.:
12/362417
Inventors:
Guo Jun Ren - San Jose CA, US
Qi Zhang - Chandler AZ, US
Ketan Sodha - Fremont CA, US
Assignee:
XILINX, INC. - San Jose CA
International Classification:
H03K 19/094
H03K 19/0175
US Classification:
326 86, 326 90, 326115
Abstract:
A method and apparatus to reduce the degradation in performance of semiconductor-based devices due to process, voltage, and temperature (PVT) and/or other causes of variation. Adaptive feedback mechanisms are employed to sense and correct performance degradation, while simultaneously facilitating configurability within integrated circuits (ICs) such as programmable logic devices (PLDs). A voltage-feedback mechanism is employed to detect PVT variation and mirrored current references are adaptively adjusted to track and substantially eliminate the PVT variation. More than one voltage-feedback mechanism may instead be utilized to detect PVT-based variations within a differential device, whereby a first voltage-feedback mechanism is utilized to detect common-mode voltage variation and a second voltage-feedback mechanism produces mirrored reference currents to substantially remove the common-mode voltage variation and facilitate symmetrical operation of the differential device. Edge boosting modules are employed to improve performance during reduced output common mode voltage modes of operation.

Input/Output Block And Operation Thereof

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US Patent:
8018250, Sep 13, 2011
Filed:
Oct 19, 2010
Appl. No.:
12/907850
Inventors:
Matthew H. Klein - Redwood City CA, US
Jian Tan - Fremont CA, US
Ketan Sodha - Fremont CA, US
Madan M. Patra - Santa Clara CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
H03K 19/00
H03K 19/02
US Classification:
326 56, 326 30, 710302, 710304
Abstract:
An embodiment of a method for operation of an input/output block is disclosed. For this embodiment of the method, a first attribute is set for a first disable signal for an input driver. A first tri-state condition is removed from an output driver. In response to the removing of the first tri-state condition, the input driver is placed in a second tri-state condition.

Method And Apparatus For A Process, Voltage, And Temperature Variation Tolerant Semiconductor Device

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US Patent:
8222954, Jul 17, 2012
Filed:
Jan 29, 2009
Appl. No.:
12/362412
Inventors:
Guo Jun Ren - San Jose CA, US
Qi Zhang - Chandler CA, US
Ketan Sodha - Fremont CA, US
Assignee:
Xilinx, Inc. - San Jose CA
International Classification:
G05F 1/10
G05F 3/02
US Classification:
327539, 327541, 323312, 323315, 323317
Abstract:
A method and apparatus to reduce the degradation in performance of semiconductor-based devices due to process, voltage, and temperature (PVT) and/or other causes of variation. Adaptive feedback mechanisms are employed to sense and correct performance degradation, while simultaneously facilitating configurability within integrated circuits (ICs) such as programmable logic devices (PLDs). A voltage-feedback mechanism is employed to detect PVT variation and mirrored current references are adaptively adjusted to track and substantially eliminate the PVT variation. More than one voltage-feedback mechanism may instead be utilized to detect PVT-based variations within a differential device, whereby a first voltage-feedback mechanism is utilized to detect common-mode voltage variation and a second voltage-feedback mechanism produces mirrored reference currents to substantially remove the common-mode voltage variation and facilitate symmetrical operation of the differential device.
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Ketan Anisha Sodha from Fremont, CA, age ~56 Get Report