Kenneth J Stern

6429712, Aug 6, 2002

Aug 29, 2001

09/941875

Thomas A. Gaiser - Amherst NH
Kenneth J. Stern - Newton MA
Farhad Vazehgoo - Tynesborough MA
Vincenzo DiTommaso - Arlington MA
William L. Walter - Lowell MA
Edward B. Hilton - Wayland MA

Analog Devices, Inc. - Norwood MA

H03K 3037

327217, 327222, 327199

A precision SET-RESET logic circuit and operating method separate a latch function from the critical signal path which produces the logic outputs. In a particular implementation the logic circuit includes two differential switch pairs controlled respectively by SET and RESET inputs, with respective enable circuits for the differential pair controlled by the output of the latch circuit. The SET and RESET differential switch pairs respond faster than the latch circuit to a change to the input SET-RESET state. A logic output is initially produced by establishing a first current path through. the differential switches and enable circuits in response to a new logic input, and then latched via a different current path.

6774694, Aug 10, 2004

Dec 24, 2002

10/328637

Kenneth J. Stern - Watertown MA
Jeff W. Barrell - Newton MA
Paul S. Cheung - North Andover MA
Thomas Alan Gaiser - Amherst NH

Analog Devices, Inc. - Norwood MA

H03H 1126

327276, 327284, 327294

A timing vernier applies a pair of stable bias voltages to intermediate points of an impedance string to establish reliable and calibratable delay cell biases for a fine multiplexer. A coarse input multiplexer is switched to a new timing signal substantially immediately after passing a prior valid timing signal to maximize the time prior to each valid output that the waveform is independent of the prior delay pattern. Logic circuitry is provided for three different phase differential regimes between successive timing signals to ensure that invalid output signals separated by less than a clock period are not produced. Mask commands are inserted into a series of timing control commands to equalize the average rates of writing and reading out the timing control commands with the mask commands skipped at readout.

7050919, May 23, 2006

Nov 19, 2003

10/718215

Kenneth Stern - Watertown MA, US

Analog Devices, Inc. - Norwood MA

G06F 19/00
H03H 11/26
G01C 23/00

702106, 3241581, 327262, 341122, 702 79

A method for autocalibrating a plurality of phase-delayed clock signal edges within a reference clock period includes measuring delay spacing between the plurality of clock signal edges, calculating programmed delay spacing, calculating ideal signal edges from the programmed delay spacing and adjusting the clock signal edges to match the respective ideal signal edges. A plurality of calibrated clock signal edges is produced that are selectively available to a user.

7272526, Sep 18, 2007

Apr 6, 2006

11/400447

Kenneth Stern - Watertown MA, US

Analog Devices, Inc. - Norwood MA

G06F 19/00
H03L 7/00
G01R 35/00

702106, 327161, 327293, 702 79

An apparatus for measuring the time delay between adjacent clock edges includes target and delay signal paths, a variable delay module in said delay signal path, the delay cell having a delay bias input, and a phase detector having respective inputs coupled to the target and delay signal paths. The variable delay module is operable to delay a first clock signal on the delay path so that a bias input signal presented to the delay bias input, when a bias input signal is present, corresponds to the time delay between the first clock signal and a second clock signal on the target signal path.

20060184333, Aug 17, 2006

Apr 6, 2006

11/400511

Kenneth Stern - Watertown MA, US

G01R 35/00

702106000

A method of calibrating a timing vernier includes autocalibrating a plurality phase-delayed clock signal edges to match respective ideal signal edges, the phase-delayed clock signal edges dividing one period of a reference clock, comparing a vernier clock signal edge to one of the plurality of phase-delayed clock signal edges after the phase-delayed clock signal edges have been autocalibrated, and adjusting the vernier clock signal edge to match the one phase-delayed clock signal edge so that the clock edge is calibrated and available for calibrated use by a user.

62659014, Jul 24, 2001

Nov 24, 1999

9/448121

Kenneth J. Stern - Newton MA
Vincenzo DiTommaso - Arlington MA

Analog Devices, Inc. - Norwood MA

H03K 19086

326126

A high speed, multiple input restrictive OR circuit with fully differential inputs and output is used in applications in which only one input can be active at a time. N differential voltage inputs are converted into N corresponding differential current signals of unit current values. The current signals corresponding to active complement input signals are summed together, with a compensation current equal to (N-1) current units subtracted from the total. The resulting compensated complement currents together with any active input current form a single differential current that indicates the logic state at the input. This differential current is preferably converted to a buffered output differential voltage in an output stage. For high accuracy applications, a common unit reference current is used to generate both a scaled compensation current and unit input stage source currents.

62429590, Jun 5, 2001

Dec 2, 1999

9/453148

Kenneth J. Stern - Newton MA

Analog Devices, Inc. - Norwood MA

H03H 1126

327262

One or more main programmed delay circuits (PDCs) are compensated to provide constant delays despite variations in environmental factors, such as temperature and power supply, by means of a dummy PDC that emulates the main PDCs in environmental sensitivity. While the main PDCs have dynamically changing programmed inputs, the dummy PDC has a constant programmed input. Changes in the dummy PDC's delay due to environmental changes are monitored and a correction signal is applied to the dummy PDC to maintain its delay substantially constant, with the same correction provided to the main PDCs to correct for the same changes in the delay of these circuits. The dummy PDC is preferably initially calibrated so that its fixed delay period coincides with an integer number of clock periods. Both the main and dummy PDCs preferably produce respective delays equal to the linear sum of a programmed delay and their correction delays.

63268280, Dec 4, 2001

Dec 7, 1999

9/456748

Thomas A. Gaiser - Amherst NH
Kenneth J. Stern - Newton MA
Farhad Vazehgoo - Tynesborough MA
Vincenzo DiTommaso - Arlington MA
William L. Walter - Lowell MA
Edward B. Hilton - Wayland MA

Analog Devices, Inc. - Norwood MA

H03K 3037

327217

A precision SET-RESET logic circuit and operating method separate a latch function from the critical signal path which produces the logic outputs. In a particular implementation the logic circuit includes two differential switch pairs controlled respectively by SET and RESET inputs, with respective enable circuits for the differential pair controlled by the output of the latch circuit. The SET and RESET differential switch pairs respond faster than the latch circuit to a change to the input SET-RESET state. A logic output is initially produced by establishing a first current path through the differential switches and enable circuits in response to a new logic input, and then latched via a different current path.