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Karan Rajani Phones & Addresses

  • San Jose, CA
  • Santa Clara, CA
  • Milpitas, CA
  • Tempe, AZ
  • Tucson, AZ

Work

Company: Maxim integrated Aug 2020 Position: Senior member of technical staff - eda

Education

Degree: Master of Science, Masters School / High School: Arizona State University 2012 to 2014 Specialities: Electrical Engineering

Skills

Verilog • Vlsi • Cadence Virtuoso • Mixed Signal • Analog • Vhdl • Cadence Spectre • Pspice • C • Tcl • Soc • Perl • Integrated Circuit Design • Microcontrollers • Semiconductors • C++ • Matlab • Unix • Modelsim • Fpga Prototyping • Analog Circuit Design • Cmos

Languages

English • Hindi

Industries

Semiconductors

Resumes

Resumes

Karan Rajani Photo 1

Senior Member Of Technical Staff - Eda

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Location:
2025 Gateway Pl, San Jose, CA 95110
Industry:
Semiconductors
Work:
Maxim Integrated
Senior Member of Technical Staff - Eda

Dolphin Technology Jun 2014 - Jan 2016
Design Engineer

Arizona State University Aug 2012 - May 2014
Graduate Student

Arizona State University Aug 2013 - May 2014
Grader

Texas Instruments May 2013 - Jul 2013
Design Engineer Intern
Education:
Arizona State University 2012 - 2014
Master of Science, Masters, Electrical Engineering
Manipal Academy of Higher Education 2007 - 2011
Bachelor of Engineering, Bachelors, Communication, Electronics
St Marks Senior Secondary Public School 1995 - 2007
Skills:
Verilog
Vlsi
Cadence Virtuoso
Mixed Signal
Analog
Vhdl
Cadence Spectre
Pspice
C
Tcl
Soc
Perl
Integrated Circuit Design
Microcontrollers
Semiconductors
C++
Matlab
Unix
Modelsim
Fpga Prototyping
Analog Circuit Design
Cmos
Languages:
English
Hindi
Karan Rajani Photo 2

Karan Rajani Tempe, AZ

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Work:
Texas Instruments
Tucson, AZ
May 2013 to Jul 2013
Design Engineer Intern in Digital to Analog converter team

Freescale Semiconductor

Jan 2011 to Jun 2011
Intern in Microcontroller Solutions Group

Alcatel - Lucent

Jun 2010 to Jul 2010
Summer Trainee

I.B.M

Jun 2009 to Jul 2009
Summer Intern

Education:
Manipal University
May 2011
Bachelor of Engineering in Electronics and Communication Engineering

Arizona State University
Tempe, AZ
Master of Science

Arizona State University
Karan Rajani Photo 3

Karan Rajani Tempe, AZ

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Work:
Texas Instruments

May 2013 to Jul 2013
Design Engineer Intern in Digital to Analog Converter (DAC) group

Freescale Semiconductor

Jan 2011 to Jun 2011
Intern in Microcontroller Solutions Group (MSG) in the Front-end (F.E) Integration team.

Alcatel - Lucent

Jun 2010 to Jul 2010
Summer Trainee

I.B.M

Jun 2009 to Jul 2009
Summer Intern

Education:
Arizona State University
Tempe, AZ
2012 to 2014
Master of Science in Electrical Engineering

Manipal University
2007 to 2011
Bachelor of Engineering in Electronics and Communication Engineering

Skills:
Programming Skills - C++, MATLAB, VHDL(VHSIC hardware description language), Verilog, TCL, Perl. Technical software - Xilinx, Model Sim 6.5, Cadence(Virtuoso, Spectre, Schematics/Spice, Encounter, RTL compiler), P-Spice, H-Spice, PLECS. Other Skills - FPGA Emulation, Validation, Evaluation Module testing.
Karan Rajani from San Jose, CA, age ~34 Get Report