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Kai R Schleupen

from Yorktown Heights, NY
Age ~60
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Also known as:
Kia N
Phone and address:
177 California Rd, Yorktown Hgts, NY 10598
(347) 524-0345
Related to:
Bill A LynchGunda RomesburyMargarete U Lynch, 65Rosemarie M Schleupen, 63Ursula Emmert, 90
Connected to:
Mark L Schleupner, 57Michael W Schleusner, 34Stanley L Schleuter, 85Becky M Schlevensky, 49Bernice A Schleve, 72Michael D Schlevenick, 72Andrew J Schlewitz, 64Diana R Schley, 97Donald B Schley, 77Douglas A Schley, 82

Kai Schleupen Phones & Addresses

  • 177 California Rd, Yorktown Heights, NY 10598 (347) 524-0345
  • Yorktown Hts, NY
  • Windham, NY
  • 137 Villa At The Woods, Peekskill, NY 10566
  • Basking Ridge, NJ
  • Greene, NY
  • Yorktown Hts, NY
  • 177 California Rd, Yorktown Heights, NY 10598

Work

Company: Ibm Position: Electrical engineer ph.d , researcher

Industries

Information Technology And Services

Resumes

Resumes

Kai Schleupen Photo 1

Electrical Engineer Ph.d , Researcher

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Location:
Yorktown Heights, NY
Industry:
Information Technology And Services
Work:
Ibm
Electrical Engineer Ph.d , Researcher

Publications

Us Patents

Passive Liquid Crystal Display Having Pre-Tilt Control Structure And Light Absorbent Material At A Center

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US Patent:
6400440, Jun 4, 2002
Filed:
Jun 23, 1999
Appl. No.:
09/339263
Inventors:
Evan G. Colgan - Chestnut Ridge NY
Shui-Chih A. Lien - Briarcliff Manor NY
Kai R. Schleupen - Yorktown Heights NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G02F 11337
US Classification:
349160, 349110, 349129, 349191
Abstract:
In accordance with the present invention, a passive liquid crystal display cell includes a first substrate having a light absorbent material patterned thereon. A first conductive material is formed in a position relative to the light absorbent material for forming one of a data line and a gate line. The position may be over the light absorbent material or below the light absorbent material (and may include transparent layers in between). A second conductive material is spaced apart from the first conductive material by a gap. The gap includes liquid crystal, and the second conductive material forms the other of the data line and the gate line. A pretilt control structure is formed adjacent to the liquid crystal. The gate line and the data line provide an electric field therebetween wherein the pretilt control structure provides pretilt for the liquid crystal to provide a wide viewing angle.

Method Of Forming Fully Self-Aligned Tft With Improved Process Window

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US Patent:
6403407, Jun 11, 2002
Filed:
Jun 2, 2000
Appl. No.:
09/586400
Inventors:
Paul Stephen Andry - Mohegan Lake NY
Evan George Colgan - Chestnut Ridge NY
Hisanori Kinoshita - Kusatsu, JP
Hiroaki Kitahara - Ohtsu, JP
Frank R. Libsch - White Plains NY
Kai R. Schleupen - Yorktown Heights NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2100
US Classification:
438158, 438151, 438159, 438160
Abstract:
A method for opening resist in raised areas of a semiconductor device. In one aspect, a conductive layer is formed over a channel insulator layer to form a raised portion including a height above a substantially planar surrounding area, the channel insulator layer being aligned to a gate electrode. A photoresist layer is formed over the raised portion and the surrounding area, and patterned by employing a gray scale light mask to reduce exposure light on the photoresist over the raised portion. Then, the photoresist is etched to thin it such that a gap is formed in the photoresist down to the conductive layer over the raised portion, but the photoresist remains everywhere else, and the conductive layer is etched in accordance with the photoresist to form source and drain electrodes which are self aligned to the channel insulator layer.

Multiplexing Pixel Circuits

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US Patent:
6414665, Jul 2, 2002
Filed:
Nov 4, 1998
Appl. No.:
09/186018
Inventors:
Frank R. Libsch - White Plains NY
Shui-Chih A. Lien - Briarcliff Manor NY
Kai R. Schleupen - Yorktown Heights NY
Robert L. Wisnieff - Ridgefield CT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G09G 336
US Classification:
345 92, 345 93, 349 42
Abstract:
An active matrix display in accordance with the present invention includes a plurality of pixels arranged in an array. At least two transistors associated with each pixel are included. The transistors are serially connected to each other and disposed within the array for switching the pixels on and off according to data and gate signals. A data line is coupled to a first end of the serially connected transistors for each pixel. A second end of the serially connected transistors is coupled to a storage device. The serially connected transistors provide multiplexing capability for at least one of data signal multiplexing and gate signal multiplexing.

Method Of Forming Fully Self-Aligned Tft Improved Process Window

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US Patent:
6429058, Aug 6, 2002
Filed:
Jun 2, 2000
Appl. No.:
09/585767
Inventors:
Evan George Colgan - Chestnut Ridge NY
Hisanori Kinoshita - Kusatsu, JP
Hiroaki Kitahara - Ohtsu, JP
Kai R. Schleupen - Yorktown Heights NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2184
US Classification:
438158, 438197, 438299
Abstract:
A method for opening resist in raised areas of a semiconductor device, in accordance with the present invention, includes forming a conductive layer over a channel insulator layer to form a raised portion which includes a height above a substantially planar surrounding area. The channel insulator layer is aligned to a gate electrode. A photoresist layer is formed over the raised portion and the surrounding area and the photoresist is patterned by employing a gray scale light mask to reduce exposure light on the photoresist on the conductive layer over the raised portion such that after developing the photoresist, the photoresist is removed over a top surface of the raised portion but remains in the surrounding area. The conductive layer is etched in accordance with the photoresist to form source and drain electrodes which are self aligned to the channel insulator layer.

Multiplexing Pixel Circuits

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US Patent:
6476787, Nov 5, 2002
Filed:
Nov 4, 1998
Appl. No.:
09/186313
Inventors:
Frank R. Libsch - White Plains NY
Kai R. Schleupen - Yorktown Heights NY
Robert L. Wisnieff - Ridgefield CT
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
G09G 336
US Classification:
345 92, 345 87, 345100, 345204, 349 48, 349139
Abstract:
An active matrix display in accordance with the present invention includes a plurality of pixels arranged in an array. At least two transistors are included for coupling to each pixel, and the transistors are positioned within the array for switching the pixels on and off according to data and gate signals. A plurality of control lines are coupled to the transistors of each pixel such that the control lines provide multiplexing for at least one of data signal multiplexing and gate signal multiplexing.

Thin Film Transistors With Self-Aligned Transparent Pixel Electrode

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US Patent:
6511869, Jan 28, 2003
Filed:
Dec 5, 2000
Appl. No.:
09/730218
Inventors:
Evan G. Colgan - Chestnut Ridge NY
Kai R. Schleupen - Yorktown Heights NY
Takatoshi Tsujimura - Kanagawa, JP
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2100
US Classification:
438149, 438150, 438159
Abstract:
A pixel cell has a thin film transistor structure formed on a substrate. A signal conductor is patterned on the thin film transistor structure, and a first patterned layer of a transparent conductive material covers the signal conductor. The first patterned layer provides a pattern employed in etching a channel region of the thin film transistor structure. A dielectric layer is formed over the pixel cell and includes a via hole down to the first patterned layer of the transparent conductive material. A second layer of transparent conductive material extends through the via hole to contact the first patterned layer wherein the second layer is self-aligned to the transistor structure.

Low Resistance Wiring In The Periphery Region Of Displays

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US Patent:
6525342, Feb 25, 2003
Filed:
May 23, 2001
Appl. No.:
09/863740
Inventors:
Takahisa Amemiya - Yamato, JP
Toshiaki Arai - Yokohama, JP
Evan George Colgan - Chestnut Ridge NY
Yoshitami Sakaguchi - Hadano, JP
Kazumi Sakai - Moriyama, JP
Kai R. Schleupen - Yorktown Heights NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2904
US Classification:
257 59, 257 57, 257383, 257384, 257408, 257751
Abstract:
A display device comprises a gate metal and a data metal formed in an array region and in a periphery region outside of the array region of the display device. A planarizing layer is formed over the array region and the periphery region. Vias are patterned into the planarizing layer in the array region and the periphery region to expose portions of at least one of the gate metal and the data metal. A transparent conductor is deposited in the array region and the periphery region. A metal layer is locally deposited over the transparent conductor in selected areas of the periphery region. The metal layer and the transparent conductor are patterned to form an additional wiring level and/or to form connections between the gate metal and the data metal in the periphery region and to form transparent pixel electrodes in the array region.

Thin Film Transistor Formed By An Etching Process With High Anisotropy

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US Patent:
6693297, Feb 17, 2004
Filed:
Jun 18, 2001
Appl. No.:
09/884726
Inventors:
Takatoshi Tsujimura - Fujisawa, JP
Masatomo Takeichi - Shiga-ken, JP
Kai R. Schleupen - Yorktown Heights NY
Evan G. Colgan - Chestnut Ridge NY
Assignee:
International Business Machines Corporation - Armonk NY
International Classification:
H01L 2904
US Classification:
257 59, 257 61, 257 66, 257 72, 257347
Abstract:
The present invention discloses a thin film transistor and a process for forming thereof by a high anisotropy etching process. A thin film transistor according to the present invention comprises a transistor element including a gate electrode, a gate insulating layer, a semiconductor layer, and source and drain electrodes; a passivation layer being deposited on the layers and having first openings for contact holes; and an interlayer insulator extending along with the passivation layer and having second openings for the contact holes, the first openings and the second openings being aligned each other over the substrate, wherein an electrical conductive layer is deposited on an inner wall of the contact hole and the inner wall is formed by the first and second openings tapered smoothly and continuously through an anisotropic etching process.
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Kai R Schleupen from Yorktown Heights, NY, age ~60 Get Report