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Juliana Manoliu

from Redwood City, CA
Age ~79
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Also known as:
Julianna Manoliu
Related to:
J Manoliu, 79
Connected to:
Albena K Manolova, 55Emil D Manolov, 39Petar Z Manolov, 47Thekla A Manoloudis, 40Paul A Manolukas, 96Veronica Manomat, 67Aida S Manon, 42Alex Manon, 53Erika Manon, 35Jennifer M Manon, 48

Juliana Manoliu Phones & Addresses

  • Redwood City, CA
  • 2761 South Ct, Palo Alto, CA 94306
  • 1150 Pine St, Menlo Park, CA 94025
  • Chase City, VA
  • PO Box 60735, Palo Alto, CA 94306

Work

Position: Food Preparation and Serving Related Occupations

Education

Degree: Associate degree or higher

Emails

j***[email protected]

Resumes

Resumes

Juliana Manoliu Photo 1

Owner

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Location:
Palo Alto, CA
Industry:
Semiconductors
Work:
Ulsi Technology Consulting
Owner
Education:
University Politehnica of Bucharest
Juliana Manoliu Photo 2

Principal

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Location:
Palo Alto, CA
Industry:
Electrical/Electronic Manufacturing
Work:
Ulsi Technology Consulting
Principal

Business Records

Name / Title
Company / Classification
Phones & Addresses
Juliana Manoliu
Owner
Exrom Real Estate
Real Estate Agent/Manager
750 University Ave, Los Gatos, CA 95032
Palo Alto, CA 94306

Publications

Us Patents

Method Of Forming Self-Registering Source, Drain, And Gate Contacts For Fet Transistor Structures

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US Patent:
43052002, Dec 15, 1981
Filed:
Nov 6, 1979
Appl. No.:
6/091845
Inventors:
John L. Moll - Palo Alto CA
Juliana Manoliu - Palo Alto CA
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
H01L 21283
US Classification:
29571
Abstract:
The present invention provides a silicon gate FET and associated integrated circuit structure in which a second level of polysilicon is selectively oxidized to provide insulating regions where desired. Regions of the polysilicon which were not oxidized are suitably doped to function as electrical interconnects to the source and drain regions in the substrate and to the gate. In the preferred embodiment, a metallic interconnection is made between the gate and drain or source region with the second level of polysilicon.

Method Of Fabricating High Performance Bicmos Structures Having Poly Emitters And Silicided Bases

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US Patent:
47270462, Feb 23, 1988
Filed:
Jul 16, 1986
Appl. No.:
6/887007
Inventors:
Prateep Tuntasood - San Jose CA
Juliana Manoliu - Palo Alto CA
Assignee:
Fairchild Semiconductor Corporation - Cupertino CA
International Classification:
H01L 2972
H01L 2704
US Classification:
437 54
Abstract:
A process is disclosed for simultaneously fabricating bipolar and complementary field effect transistors. The process enables distinguishing the bipolar devices from the CMOS devices with a single base mask 108, while requiring only a single additional mask 114 to define the bipolar emitter and MOS gates. The process forms the gate oxide 100 for the MOS devices at an early stage, then protects that oxide with polysilicon 103 during subsequent fabrication steps. Self-aligned metal silicide contacts 137 are separated from undesired regions using sidewall oxidation techniques.

Smaller Memory Cells And Logic Circuits

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US Patent:
43203124, Mar 16, 1982
Filed:
Oct 2, 1978
Appl. No.:
5/947377
Inventors:
Laurence G. Walker - Palo Alto CA
James D. Sansbury - Portola Valley CA
Robert D. Rung - Menlo Park CA
Juliana Manoliu - Palo Alto CA
Assignee:
Hewlett-Packard Company - Palo Alto CA
International Classification:
H03K 500
H03K 1760
H01L 2978
US Classification:
3072388
Abstract:
A method and device are disclosed for reducing the circuit size of a class of circuits including many memory cells and logic circuits. Selected drain to bulk or source to bulk transistor junctions are made leaky. The leaky junctions perform their intended (non-leaky) functions as well as the functions of certain other circuit elements. These other elements may therefore be eliminated from the circuit.

Method For Simultaneously Fabricating Bipolar And Complementary Field Effect Transistors Using A Minimal Number Of Masks

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US Patent:
50231936, Jun 11, 1991
Filed:
Oct 3, 1988
Appl. No.:
7/253946
Inventors:
Juliana Manoliu - Palo Alto CA
Prateep Tuntasood - San Jose CA
Assignee:
National Semiconductor Corp. - Santa Clara CA
International Classification:
H01L 21331
US Classification:
437 31
Abstract:
A process is disclosed for simultaneously fabricating bipolar and complementary field effect transistors. The process includes the fabrication of buried layers 18 doped with both phosphorus and arsenic to permit a shorter diffusion time while simultaneously providing buried layers having low resistance and high diffusivity. The process enables fabrication of BiCMOS structures using only six masks prior to the contact mask.

Method For Simultaneously Fabricating Bipolar And Complementary Field Effect Transistors

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US Patent:
54078407, Apr 18, 1995
Filed:
Aug 4, 1992
Appl. No.:
7/925807
Inventors:
Juliana Manoliu - Palo Alto CA
Prateep Tuntasood - San Jose CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 21328
H01L 21336
US Classification:
437 31
Abstract:
A process is disclosed for simultaneously fabricating bipolar and complementary field effect transistors. The process includes the fabrication of buried layers 18 doped with both phosphorus and arsenic to permit a shorter diffusion time while simultaneously providing buried layers having low resistance and high diffusivity. The process enables fabrication of BiCMOS structures using only six masks prior to the contact mask. The process also comprises oxidizing an epitaxial layer for forming a differential thickness oxide layer which is thicker over the source and drain regions, the collector contact and the emitter than over the base contact region.

Controlled Temperature Polycrystalline Silicon Nucleation

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US Patent:
40875717, May 2, 1978
Filed:
Jun 24, 1975
Appl. No.:
5/589821
Inventors:
Theodore I. Kamins - Mountain View CA
Juliana Manoliu - Palo Alto CA
Assignee:
Fairchild Camera and Instrument Corporation - Mountain View CA
International Classification:
H01L 21205
US Classification:
427 86
Abstract:
The diffusivity of an impurity in a layer of polycrystalline silicon is controlled by forming the polycrystalline silicon on a thin nucleating layer of polycrystalline silicon possessing a maximum {110} texture.

Cmos And Bipolar Fabrication Process Using Selective Epitaxial Growth Scalable To Below 0.5 Micron

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US Patent:
50100343, Apr 23, 1991
Filed:
Mar 7, 1989
Appl. No.:
7/320011
Inventors:
Juliana Manoliu - Palo Alto CA
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H01L 2120
US Classification:
437 89
Abstract:
A CMOS and bipolar fabrication process wherein a silicon dioxide layer initially formed over a silicon substrate is etched for forming separate collector and base/emitter regions for a bipolar device, and PMOS and NMOS regions for corresponding PMOS and NMOS devices. Buried layer implants are performed using a minimum number of masks, and then an epitaxial layer is grown over the exposed portions of the silicon substrate. The silicon dioxide walls between the devices provide full dielectric isolation between the devices, as well as between the collector and base/emitter regions of the bipolar device. Nonetheless, the oxide wall between the collector and base/emitter of the bipolar device is sufficiently small to allow the buried layer implants to joint under the wall for forming a conventional buried layer for the bipolar device. Because of the oxide walls, the minimum distance between devices may be 0. 5 microns or less.
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Juliana Manoliu from Redwood City, CA, age ~79 Get Report