Judith M Linger

59681586, Oct 19, 1999

Oct 6, 1997

8/944209

Lawrence P. Andrews - Boca Raton FL
Richard Clyde Beckman - Boca Raton FL
Robert Chih-Tsin Eng - Boca Raton FL
Judith Marie Linger - Delray Beach FL
Joseph C. Petty - Boca Raton FL
John Claude Sinibaldi - Pompano Beach FL
Gary L. Turbeville - Boca Raton FL
Kevin Bradley Williams - Plantation FL

International Business Machines Corporation - Armonk NY

G06F 946

710260

A pair of communications adapters each include a number of digital signal processors and network interface circuits for the attachment of a multi-channel telephone line. A bus connecting the communications adapters can carry data between a network line attached to one of the adapters and the digital signal processors of the other adapter. The digital signal processors on each card are connected to a host, or controller, processor. Each digital signal processor interrupts its host processor by transmitting an interrupt control block as data to a data memory of the host processor, and by subsequently sending an interrupt causing the host processor to examine the data memory. Preferably, the interrupt control block includes data representing a number of requested interrupts.

55726950, Nov 5, 1996

May 31, 1994

8/250974

Lawrence P. Andrews - Boca Raton FL
Derrick L. Arias - Miami FL
Judith M. Linger - Delray Beach FL
Baiju D. Mandalia - Boca Raton FL
Oscar E. Ortega - Miami FL
John C. Sinibaldi - Pompano Beach FL

International Business Machines Corporation - Armonk NY

G06F 1202

395412

A digital signal processing system includes first and second logical memory mapping units coupled to first and second digital processors respectively and to a data storage unit. The system further includes first and second mapping registers for containing first and second address mapping information coupled to the first and second digital processors respectively. The first and second mapping units are operative to receive (i) first and second logical addresses generated by the first and second digital processors respectively and (ii) first and second address mapping information respectively, and generate first and second physical addresses such that each of the digital processors can independently access any of a plurality of memory locations within the data storage unit.

54917204, Feb 13, 1996

May 21, 1992

7/887433

Gordon T. Davis - Raleigh NC
Judith M. Linger - Delray Beach FL
Baiju D. Mandalia - Boca Raton FL
John C. Sinibaldi - Pompano Beach FL
William M. Zevin - Boca Raton FL
Karl-Heinz Ziegenhain - Wiesbaden, DE

International Business Machines Corporation - Armonk NY

H04B 138

375222

A method and system in a data communications system for automatically determining a data communication device type and a transmission speed associated with the data communication device type. An incoming communication is detected on a transmission line, and transmit and receive hardware are connected to the transmission line. Next, a sequence of different signals in either a first communication protocol or a second communication protocol are transmitted from a first data communication device via a transmission line. The transmission line is then monitored for a response signal from a second data communication device. The response signal is initiated from the second data communication device in response to receipt of a particular signal within the transmitted sequence of different signals. Utilizing the relationship between the response signal and the transmitted sequence of different signals, a data communication device type and transmission speed are determined, and data communications may then be established between the first data communication device and the second data communication device at an optimal transmission speed.

62336436, May 15, 2001

Jun 23, 1999

9/338611

Lawrence P. Andrews - Boca Raton FL
Richard Clyde Beckman - Boca Raton FL
Robert Chih-Tsin Eng - Boca Raton FL
Judith Marie Linger - Delray Beach FL
Joseph C. Petty - Boca Raton FL
John Claude Sinibaldi - Pompano Beach FL
Gary L. Turbeville - Boca Raton FL
Kevin Bradley Williams - Plantation FL

International Business Machines Corporation - Armonk NY

G06F 1300
G06F 1338

710131

A pair of communications adapters each include a number of digital signal processors and network interface circuits for the attachment of a multi-channel telephone line. A bus connecting the communications adapters can carry data between a network line attached to one of the adapters and the digital signal processors of the other adapter. The digital signal processors on each card are connected to a host, or controller, processor. Each digital signal processor interrupts its host processor by transmitting an interrupt control block as data to a data memory of the host processor, and by subsequently sending an interrupt causing the host processor to examine the data memory. Preferably, the interrupt control block includes data representing a number of requested interrupts.

56922078, Nov 25, 1997

Dec 14, 1994

8/355793

Michael George Ho-Lung - Boca Raton FL
Judith Marie Linger - Delray Beach FL
Baiju Dhirajlal Mandalia - Boca Raton FL
John Claude Sinibaldi - Pompano Beach FL

International Business Machines Corporation - Armonk NY

G06F 900

395800

A digital signal processing system includes a first and second memory coupled to first and second register banks respectively. The system further includes first and second multipliers coupled to the first and second register banks for producing first and second product outputs respectively. The system also includes an arithmetic logic unit having first, second and third inputs and an output. The first input is coupled to the first product output and the second and third inputs are selectively coupled to either of the second product output and the first and second register means. The arithmetic logic unit output is coupled to the first and second register banks for accumulating the sample values in the first and second register banks. The system further includes Instruction control for storing a plurality of instruction op codes and controlling the system to compute the sample values by performing simplex operations during each cycle of a plurality of operating cycles of a digital signal processing procedure.