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Joshua Sinykin Phones & Addresses

  • 21 Slocum Meadow Ln, Shrewsbury, MA 01545
  • Westborough, MA
  • 2023 Silkwood Dr, Colorado Springs, CO 80920 (719) 266-6016
  • 2935 Underwood Pt, Colorado Springs, CO 80920 (719) 599-8079
  • Colorado Spgs, CO
  • Webster, MA
  • Madison, WI
  • Minneapolis, MN

Work

Position: Clerical/White Collar

Publications

Us Patents

Methods And Systems For Integrating Unique Information In Sas Interface Components

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US Patent:
7502874, Mar 10, 2009
Filed:
Nov 21, 2006
Appl. No.:
11/562228
Inventors:
Steven F. Faulhaber - Colorado Springs CO,
Joshua P. Sinykin - Colorado Springs CO,
Matthew K. Freel - Colorado Springs CO,
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G06F 3/00
G06F 17/50
US Classification:
710 13, 710 23, 710 62, 710 74, 716 12, 711170
Abstract:
Methods and systems for customizing information in a memory associated with a SAS host bus adapter (“HBA”). A SAS HBA typically includes a memory component that stores information common to all SAS HBA's manufactured by a particular vendor (e. g. , common instructions and data). In addition, each HBA memory component typically includes some information unique to each HBA (e. g. , board trace number, SAS address, configuration page, boot record, etc. ). Features and aspects hereof permit pre-programmed memory components to be integrated with a SAS HBA to eliminate a step to program an assembled HBA through a specialized, one-time interaction to add required unique information. Thus a manufacturer may simply integrate a pre-programmed memory component to an otherwise completed HBA assembly to complete the product manufacturing without need for a special programming step. Or a design or test engineer may simply replace a memory component to change unique information on the HBA.

Methods And Systems For Integrating Unique Information In Sas Interface Components

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US Patent:
7636798, Dec 22, 2009
Filed:
Jan 26, 2009
Appl. No.:
12/359446
Inventors:
Steven F. Faulhaber - Bloomington MN,
Joshua P. Sinykin - Colorado Springs CO,
Matthew K. Freel - Colorado Springs CO,
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G06F 3/00
G06F 17/50
US Classification:
710 13, 710 23, 710 62, 710 74, 716 12, 711170
Abstract:
Methods and systems for customizing information in a memory associated with a SAS host bus adapter (“HBA”). A SAS HBA typically includes a memory component that stores information common to all SAS HBA's manufactured by a particular vendor (e. g. , common instructions and data). In addition, each HBA memory component typically includes some information unique to each HBA (e. g. , board trace number, SAS address, configuration page, boot record, etc. ). Features and aspects hereof permit pre-programmed memory components to be integrated with a SAS HBA to eliminate a step to program an assembled HBA through a specialized, one-time interaction to add required unique information. Thus a manufacturer may simply integrate a pre-programmed memory component to an otherwise completed HBA assembly to complete the product manufacturing without need for a special programming step. Or a design or test engineer may simply replace a memory component to change unique information on the HBA.

Serial Input Output (Sio) Port Expansion Apparatus And Method

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US Patent:
8521931, Aug 27, 2013
Filed:
Dec 30, 2010
Appl. No.:
12/981847
Inventors:
Joshua P. Sinykin - Shrewsbury MA,
William K. Petty - Colorado Springs CO,
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G06F 13/00
G06F 13/12
US Classification:
710110, 710 71, 710 74, 710300
Abstract:
An expander device and method for transmitting serial input/output (SIO) data between an initiator device and a plurality of target devices. The expander device includes a processor/controller configured to receive a master data stream from an initiator device and to transmit a returning master data stream to the initiator device. The expander device includes a plurality of target master ports coupled to the processor/controller and configured to transmit split data streams to corresponding target devices coupled thereto and to receive returning split data streams from the target devices. The processor/controller splits the master data stream, based on its data, into a plurality of split data streams, and directs the split data streams to the target master ports based on the data in the split data streams. The processor/controller also assembles a plurality of returning split data streams into the returning master data stream and transmits the returning master data stream to the initiator device.

Methods And Structure For Storing Errors For Error Recovery In A Hardware Controller

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US Patent:
8589722, Nov 19, 2013
Filed:
May 9, 2011
Appl. No.:
13/103623
Inventors:
Joshua P. Sinykin - Shrewsbury MA,
Jeffrey K. Whitt - Colorado Springs CO,
Assignee:
LSI Corporation - Milpitas CA
International Classification:
G06F 11/00
US Classification:
714 41, 714 2
Abstract:
Methods and structure for providing methods and structure for recovering errors in a hardware controller after an overwrite event, such as the detection of another error. In this regard, a link layer of the hardware controller is configured with a register that persistently stores errors until a processor can address them. The link layer is adapted to establish a connection between an initiator and a target and detect errors associated with the connection. As each detected error is overwritten by a subsequently detected error, the link layer register persistently stores the detected errors associated with the connection for recovery after the detected error has been overwritten in the link layer at least until the error can be handled.

Methods And Structure For Sas Domain Transceiver Optimization

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US Patent:
20070087615, Apr 19, 2007
Filed:
Oct 14, 2005
Appl. No.:
11/251393
Inventors:
Erik Paulsen - Colorado Springs CO,
Joshua Sinykin - Colorado Springs CO,
Gabriel Romero - Colorado Springs CO,
International Classification:
H01R 13/64
US Classification:
439378000
Abstract:
Methods and structures within a SAS domain for automated tuning performance of a coupled pair of transceivers. In one aspect hereof, control registers of a transmitting transceiver coupled to a receiving transceiver are adjusted to a plurality of distinct combinations of settings. For each distinct setting, a test pattern may be transmitted from the transmitting transceiver to the receiving transceiver. Status registers of the transmitting transceiver and of the receiving transceiver may be read to identify errors in the transmission. Identified errors are counted for each for distinct setting of the control registers to determine a preferred setting to best tune operation of the transceiver pair. The testing may be performed by any SAS initiator device or SAS expander acting as an initiator and may be performed on any coupled pair of transceiver in the SAS domain.

System And Method For Amplitude Optimization In High-Speed Serial Transmissions

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US Patent:
20070121496, May 31, 2007
Filed:
Nov 30, 2005
Appl. No.:
11/290786
Inventors:
Joshua Sinykin - Colorado Springs CO,
Gabriel Romero - Colorado Springs CO,
International Classification:
H04L 12/26
H04B 1/44
US Classification:
370229000, 370282000
Abstract:
A method, system, and computer usable program code for increasing drive strength using various steps. First, a data signal is received at a receiving device. The receiving device determines whether the data is successfully received once the data signal is received at the receiving device. If the receiving device determines that the data signal is unsuccessfully received, the receiving device requests an increase in a signal amplitude of the data signal transmitted by a transmitting device that sent the data signal for increasing the drive strength.

Methods And Apparatus For Distribution Of Raid Storage Management Over A Sas Domain

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US Patent:
20110145452, Jun 16, 2011
Filed:
Dec 16, 2009
Appl. No.:
12/639853
Inventors:
Jason B. Schilling - Colorado Springs CO,
Joshua P. Sinykin - Shrewsbury MA,
Assignee:
LSI CORPORATION - Milpitas CA
International Classification:
G06F 13/00
G06F 13/38
US Classification:
710 74, 710300
Abstract:
Methods and apparatus for distributing Redundant Array of Independent Disks (RAID) storage management to one or more Serial Attached SCSI (SAS) expanders in a SAS domain. A RAID set comprises a set of one or more SAS expanders coupled to communicate with one another to process I/O requests directed to a RAID logical volume of the RAID set. The RAID logical volume is distributed over portions of each of multiple storage devices. Each SAS expander of the RAID set is coupled to one or more of the multiple storage devices. Each SAS expander of the RAID set processes a corresponding portion of a received I/O request directed to the RAID logical volume. A master SAS expander of the RAID set receives and aggregates the status information from each of the SAS expanders of the RAID set and returns a completion status to the requesting SAS initiator.

Mapping Circuit Test Logic By Analyzing Register Transfer Level Circuit Models

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US Patent:
20130179741, Jul 11, 2013
Filed:
Jan 6, 2012
Appl. No.:
13/344851
Inventors:
Joshua P. Sinykin - Shrewsbury MA,
Assignee:
LSI CORPORATION - Milpitas CA
International Classification:
G01R 31/3177
G06F 11/25
US Classification:
714724, 714E11155
Abstract:
Methods and systems for mapping and programming the debug logic of a circuit are provided. The system acquires a Register Transfer Level (RTL) representation of a circuit, wherein the circuit implements test logic that is externally programmable for providing one or more output signals corresponding to internal operational signals. The system analyzes the RTL representation to identify test multiplexers (MUXs) having registers for implementing the test logic, and correlates test register values for the test MUXs with outputs corresponding to the internal operational signals, based upon the RTL representation. The system further enables a user to select a desired internal operational signal for acquisition. Additionally, the system programs the test registers of the test MUXs of the circuit based on the correlated test register values to acquire the selected internal operational signal and to apply the acquired signal as one or more output signals.
Joshua P Sinykin from Shrewsbury, MA, age ~39 Get Report