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Josef J Ezra

from Norfolk, MA
Age ~58
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Also known as:
Joseph J Ezra, Joe J Ezra, Ezra Josef
Phone and address:
14 Brewster Rd, Norfolk, MA 02056
Connected to:
Ben B Ezra, 47Cheryl D Ezra, 61David A Ezra, 77Jonathan Ezra, 26Judy E Ezratty, 77Marla E Ezratty, 74Leslie A Ezrow, 63Guyla R Ezugha, 38Cordelia N Ezugwu, 56Cartney N Ezyk, 78

Josef Ezra Phones & Addresses

  • 14 Brewster Rd, Norfolk, MA 02056
  • Irvine, CA
  • 21 Nardone Rd, Newton Center, MA 02459 (508) 969-2070
  • Newton, MA
  • 8 Apple St, Sherborn, MA 01770
  • 145 Captain Eames Cir, Ashland, MA 01721 (508) 231-4599 (508) 969-2060

Work

Company: Emc Jan 2008 Position: Consultant engineer

Education

Degree: Masters

Industries

Information Technology And Services

Resumes

Resumes

Josef Ezra Photo 1

Consultant Engineer

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Location:
14 Brewster Rd, Norfolk, MA 02056
Industry:
Information Technology And Services
Work:
Emc
Consultant Engineer
Ben Gurion University of the Negev 1996 - 2000
Student and Staff

Business Records

Name / Title
Company / Classification
Phones & Addresses
Josef Ezra
Manager
UVIK, LLC
8 Apple St, Sherborn, MA 01770

Publications

Us Patents

Advancing Bank Pointer In Prime Numbers Unit

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US Patent:
6807619, Oct 19, 2004
Filed:
Sep 5, 2002
Appl. No.:
10/235137
Inventors:
Josef Ezra - Ashland MA
Yedidia Atzmony - Newton MA
Assignee:
EMC Corporation - Hopkinton MA
International Classification:
G06F 1200
US Classification:
711219, 711130, 711133, 711144, 711154, 711156, 711159
Abstract:
The cache arrangement includes a cache that may be organized as a plurality of memory banks in which each memory bank includes a plurality of slots. Each memory bank has an associated control slot that includes groups of extents of tags. Each cache slot has a corresponding tag that includes a bit value indicating the availability of the associated cache slot, and a time stamp indicating the last time the data in the slot was used. The cache may be shared by multiple processors. Exclusive access of the cache slots is implemented using an atomic compare and swap instruction. The time stamp of slots in the cache may be adjusted to indicate ages of slots affecting the amount of time a particular portion of data remains in the cache. Associated with each processor is a unique extent increment used to determine a next location for that particular processor when attempting to locate an available slot.

Debugging Tool For Efficient Switching Between Targets In A Multi-Processor Environment

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US Patent:
6941492, Sep 6, 2005
Filed:
Feb 5, 2002
Appl. No.:
10/068079
Inventors:
Josef Ezra - Ashland MA, US
Eli Shagam - Brookline MA, US
Assignee:
EMC Corporation - Hopkinton MA
International Classification:
G06F011/00
US Classification:
714 38, 714 27, 714 45, 714 46, 717124, 717128, 717129, 717131
Abstract:
A debugger mechanism to support multiple active targets and efficient switching between multiple active targets, in particular, heterogeneous targets, in a multiprocessing environment.

Qos Feature Knobs

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US Patent:
7047366, May 16, 2006
Filed:
Jun 17, 2003
Appl. No.:
10/463247
Inventors:
Josef Ezra - Ashland MA, US
Assignee:
EMC Corporation - Hopkinton MA
International Classification:
G06F 12/00
US Classification:
711141, 711129, 711135
Abstract:
Described are various quality of service (QOS) parameters that may be used in characterizing device behavior in connection with a cache. A Partition parameter indicates which portions of available cache may used with data of an associated device. A Survival parameter indicates how long data of an associate device should remain in cache after use. A Linearity parameter indicates a likelihood factor that subsequent data tracks may be used such that this parameter may be used in determining whether to prefetch data. A Flush parameter indicates how long data should remain in cache after a write pending slot is returned to cache after being written out to the actual device. The QOS parameters may be included in configuration data. The QOS parameter values may be read and/or modified.

Locally Buffered Cache Extensions Having Associated Control Parameters To Determine Use For Cache Allocation On Subsequent Requests

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US Patent:
7089357, Aug 8, 2006
Filed:
Sep 22, 2003
Appl. No.:
10/667564
Inventors:
Josef Ezra - Ashland MA, US
Assignee:
EMC Corporation - Hopkinton MA
International Classification:
G06F 12/00
G06F 13/00
US Classification:
711113, 711162, 711170, 711144, 711145, 714 6
Abstract:
A method and apparatus for cache management in a data storage system is presented. A table with tags corresponding to cache slots in a cache memory is provided. A copy of the table is stored in a local buffer in response to a request for allocation of one of the cache slots. The locally buffered table is used to make the requested cache slot allocation. A set of control parameters associated with the locally buffered table is used to determine if the locally buffered table can be re-used for cache slot allocation in response to a subsequent request for cache slot allocation. User-selectable levels are provided to control the degree of locally buffered table re-use. The user-selectable levels determine which values of the control parameters are used.

Method For Cache Management For Positioning Cache Slot

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US Patent:
7143393, Nov 28, 2006
Filed:
Jun 24, 2002
Appl. No.:
10/178085
Inventors:
Josef Ezra - Ashland MA, US
Daniel Lambright - Watertown MA, US
Assignee:
EMC Corporation - Hopkinton MA
International Classification:
G06F 9/44
G06F 12/00
US Classification:
717127, 717124, 717125, 717126, 717129, 711118, 711125, 711171
Abstract:
Described are techniques used in connection with cache management. Data included in a cache slot is put “on parole” with a first cache hit while waiting for subsequent cache hits. If a subsequent hit is received to the cache slot, it remains in the cache for a longer time period than a slot having only a first cache hit. The cache may be organized as a plurality of memory banks of cache slots. Each memory bank has an associated control slot that includes groups of extents of tags. Each cache slot has a corresponding tag, and a time stamp. The time stamp of slots in the cache may be adjusted affecting the amount of time a particular portion of data remains in the cache.

Cache Fall Through Time Estimation

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US Patent:
7155573, Dec 26, 2006
Filed:
May 25, 2004
Appl. No.:
10/853035
Inventors:
Josef Ezra - Ashland MA, US
Assignee:
EMC Corporation - Hopkinton MA
International Classification:
G06F 12/08
US Classification:
711133, 711145
Abstract:
A method for estimating the fall through time of a cache includes maintaining local statistics associated with each data cache slot replaced by a processor, reading from a memory global statistics related to each data cache slot replaced by a plurality of processors, calculating new global statistics, and estimating a fall through time of the cache in response to the global statistics at a predetermined rate. When the global statistics are the result of at least a threshold number of data cache slots having been replaced, the new global statistics are calculated by weighting the global statistics by a factor of less than one and adding the weighted global statistics to the local statistics. When the global statistics are not the result of at least a threshold number of data cache slots having been replaced, the new global statistics are calculated by adding a time related to the lapsed time to a global sum value associated with the time stamp difference of the replaced data cache slots. In a multi-processor computer system, each of the processors accesses the global memory to update the global statistics at a different time.

Cache Management Via Statistically Adjusted Time Stamp Queue

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US Patent:
7177853, Feb 13, 2007
Filed:
Feb 21, 2002
Appl. No.:
10/080321
Inventors:
Josef Ezra - Ashland MA, US
Yechiel Yochai - Brookline MA, US
Daniel Lambright - Watertown MA, US
Sachin More - Marlborough MA, US
Yedidia Atzmony - Newton MA, US
Assignee:
EMC Corporation - Hopkinton MA
International Classification:
G06F 17/30
US Classification:
707 1
Abstract:
Described are techniques and criteria used in connection with cache management. The cache may be organized as a plurality of memory banks in which each memory bank includes a plurality of slots. Each memory bank has an associate control slot that includes groups of extents of tags. Each cache slot has a corresponding tag that includes a bit value indicating the availability of the associated cache slot, and a time stamp indicating the last time the data in the slot was used. The cache may be shared by multiple processors. Exclusive access of the cache slots is implemented using an atomic compare and swap instruction. The time stamp of slots in the cache may be adjusted to indicate ages of slots affecting the amount of time a particular portion of data remains in the cache.

Sequential Event Monitoring Module

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US Patent:
7216336, May 8, 2007
Filed:
Feb 28, 2003
Appl. No.:
10/375991
Inventors:
Josef Ezra - Ashland MA, US
Ohad Zeliger - Westborough MA, US
Assignee:
EMC Corporation - Hopkinton MA
International Classification:
G06F 9/45
US Classification:
717124
Abstract:
A debugger mechanism that provides for debugging source code of a target by correlating messages in a log file associated with source code with corresponding lines of the source code.
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Josef J Ezra from Norfolk, MA, age ~58 Get Report